73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 54

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

73S1210F Data Sheet
1.7.12 I
The 73S1210F includes a dedicated fast mode, 400kHz I
or write 1 or 2 bytes of data per data transfer frame. The MPU communicates with the interface through
six dedicated SFR registers:
•
•
•
•
•
•
The
operation. The
the I
automatically de-asserted when a subsequent I
clock from the time-base circuits.
1.7.12.1
To write data on the I
following sequence:
1. Write slave device address to Device Address register (DAR). The data contains 7 bits for the slave
2. Write data to Write Data register (WDR). This data will be transferred to the slave device.
3. If writing 2 bytes, set bit 0 of the Control and Status register (CSR) and load the second data byte to
4. Set bit 1 of the
5. Wait for I
Figure 10
54
Device Address (DAR)
Write Data (WDR)
Secondary Write Data (SWDR)
Read Data (RDR)
Secondary Read Data (SRDR)
Control and Status (CSR)
device address and 1 bit of op-code. The op-code bit should be written with a 0 to indicate a write
operation.
Secondary Write Data register (SWDR).
information about the INT6Ctl,
2
DAR
C transaction is complete, the I
2
register is used to set up the slave address and specify if the transaction is a read or write
shows the timing of the I
C Master Interface
I
2
C Write Sequence
2
C interrupt to be asserted. It indicates that the write on I
CSR
CSR
register sets up, starts the transaction and reports any errors that may occur. When
2
C Master Bus, the 80515 has to program the following registers according to the
register to start I
2
IEN1
C write mode:
2
C interrupt is reported via external interrupt 6. The I
and
2
C Master Bus.
IRCON
2
C transaction is started. The I
register for masking and flag operation.
2
C Master interface. The I
2
C Master Bus is done. Refer to
2
C interface uses a 400kHz
2
C interface can read
2
C interrupt is
DS_1210F_001
Rev. 1.4