73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 30

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

73S1210F Data Sheet
External Interrupt Control Register (INT5Ctl): 0xFF94  0x00
Miscellaneous Control Register 0 (MISCtl0): 0xFFF1  0x00
30
MISCtl0.7
MISCtl0.6
MISCtl0.5
MISCtl0.4
MISCtl0.3
MISCtl0.2
MISCtl0.1
MISCtl0.0
INT5Ctl.7
INT5Ctl.6
INT5Ctl.5
INT5Ctl.4
INT5Ctl.3
INT5Ctl.2
INT5Ctl.1
INT5Ctl.0
Bit
Bit
MSB
MSB
PWRDN
PDMUX
PWRDN
Symbol
SLPBK
SSEL
PDMUX
Symbol
KPIEN
KPINT
–
–
–
–
–
–
–
–
–
–
–
–
This bit sets the circuit into a low-power condition. All analog (high-speed
oscillator and VCO/PLL) functions are disabled 32 MPU clock cycles after
this bit is set = 1. This allows time for the next instruction to set the STOP
bit in the
this mode. When set, this bit overrides the individual control bits that
otherwise control power consumption.
UART loop back testing mode.
Serial port pins select.
When set = 1, enables interrupts from Keypad (normally going to int5),
Smart Card interrupts (normally going to int4), or USR(7:0) pins (int0) to
cause interrupt on int0. The assertion of the interrupt to int0 is delayed by
512 MPU clocks to allow the analog circuits, including the clock system, to
stabilize. This bit must be set prior to asserting the PWRDN bit in order to
properly configure the interrupts that will wake up the circuit. This bit is
reset = 0 when this register is read.
Keypad interrupt enable.
Keypad interrupt flag.
–
–
Table 15: The MISCtl0 Register
Table 14: The INT5Ctl Register
PCON
register to stop the CPU core. The MPU is not operative in
–
–
–
–
Function
Function
–
–
SLPBK
KPIEN
KPINT
SSEL
LSB
LSB
DS_1210F_001
Rev. 1.4