73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 37

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS_1210F_001
Interrupt Request Register (IRCON): 0xC0  0x00
1.7.5.3
The external interrupts (external to the CPU core) are connected as shown in Table 25. Interrupts with
multiple sources are OR’ed together and individual interrupt source control is provided in XRAM SFRs to
mask the individual interrupt sources and provide the corresponding interrupt flags. Multifunction USR
[7:0] pins control Interrupts 0 and 1. Dedicated external interrupt pins INT2 and INT3 control interrupts 2
and 3. The polarity of interrupts 2 and 3 is programmable in the MPU. Interrupts 4, 5 and 6 have multiple
peripheral sources and are multiplexed to one of these three interrupts. The peripheral functions will be
described in subsequent sections. Generic 80515 MPU literature states that interrupts 4 through 6 are
defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 4, 5 and 6 are
converted to rising edge level by the hardware.
SFR (special function register) enable bits must be set to permit any of these interrupts to occur.
Likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically
by the MPU interrupt handler.
Note: Interrupts 4, 5 and 6 have multiple interrupt sources and the flag bits are cleared upon reading of
the corresponding register. To prevent any interrupts from being ignored, the register containing multiple
interrupt flags should be stored temporary to allow each interrupt flag to be tested separately to see which
interrupt(s) is/are pending.
Rev. 1.4
IRCON.7
IRCON.6
IRCON.5
IRCON.4
IRCON.3
IRCON.2
IRCON.1
IRCON.0
Bit
External Interrupts
Interrupt
External
MSB
Symbol
0
1
2
3
4
5
6
IEX6
IEX5
IEX4
IEX3
IEX2
–
–
–
–
USR I/O High Priority
USR I/O Low Priority
External Interrupt Pin INT2
External Interrupt Pin INT3
Smart Card Interrupts
Keypad
I
2
External interrupt 6 flag.
External interrupt 5 flag.
External interrupt 4 flag.
External interrupt 3 flag.
External interrupt 2 flag.
C, V
–
DD
_Fault, Analog Comp
Connection
Table 25: External MPU Interrupts
EX6
Table 24: The IRCON Register
IEX5
IEX4
Function
Edge selectable
Edge selectable
see
see
Polarity
USRIntCtlx
USRIntCtlx
IEX3
N/A
N/A
N/A
IEX2
Flag Reset
Automatic
Automatic
Automatic
Automatic
Automatic
Automatic
Automatic
73S1210F Data Sheet
–
LSB
37