73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 59

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS_1210F_001
I2C Secondary Read Data Register (SRDR): 0XFF84  0x00
I2C Control and Status Register (CSR): 0xFF85  0x00
Rev. 1.4
CSR.7
CSR.6
CSR.5
CSR.4
CSR.3
CSR.2
CSR.1
CSR.0
MSB
MSB
Bit
SRDR.7
SRDR.7
SRDR.6
SRDR.5
SRDR.4
SRDR.3
SRDR.2
SRDR.1
SRDR.0
Bit
–
Symbol
I2CLEN
AKERR
Second Data byte to be read from the I
and Status register (CSR) is set = 1.
I2CST
SRDR.6
–
–
–
–
–
–
Set to 1 if acknowledge bit from Slave Device is not 0. Automatically reset
when the new bus transaction is started.
Write a 1 to start I
transaction is done. This bit should be treated as a “busy” indicator on
reading. If it is high, the serial read/write operations are not completed and
no new address or data should be written.
Set to 1 for 2 byte read or write operations. Set to 0 for 1-byte operations.
SRDR.5
–
Table 61: The SRDR Register
Table 62: The CSR Register
SRDR.4
–
2
C transaction. Automatically reset to 0 when the bus
SRDR.3
Function
2
–
C slave device if bit 0 (I2CLEN) of the Control
Function
AKERR
SRDR.2
SRDR.1
I2CST
73S1210F Data Sheet
SRDR.0
I2CLEN
LSB
LSB
59