PIC18F26K80-I/SO Microchip Technology, PIC18F26K80-I/SO Datasheet - Page 324

• Manufacturer Part Number: PIC18F26K80-I/SO
• Description: MCU PIC 64KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K80-I/SO

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F26K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F66K80 FAMILY
21.4.7
In I
reload value is placed in the lower 7 bits of the
SSPADD register
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to 0 and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
Q2 and Q4 clocks. In I
reloaded automatically.
FIGURE 21-19:
TABLE 21-3:
DS39977C-page 324
Note 1:
2
C Master mode, the Baud Rate Generator (BRG)
16 MHz
2:
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
F
OSC
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
A minimum 16-MHz F
BAUD RATE
(2)
2
C interface does not conform to the 400 kHz I
(Figure
I
2
C™ CLOCK RATE w/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C Master mode, the BRG is
21-19). When a write occurs
SSPM<3:0>
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
4 MHz
SCL
F
OSC
CY
is required for 1 MHz I
SSPM<3:0>
CY
) on the
Control
Reload
Preliminary
CLKO
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
CY
* 2
Reload
2
C.
2
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 21-3
instruction cycles and the BRG value loaded into
SSPADD. The SSPADD BRG value of 00h is not
supported.
BRG Down Counter
C specification (which applies to rates greater than
SSPADD<6:0>
demonstrates clock rates based on
BRG Value
0Ch
18h
1Fh
63h
09h
27h
02h
09h
03h
 2011 Microchip Technology Inc.
F
OSC
/4
(2 Rollovers of BRG)
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
100 kHz
308 kHz
100 kHz
100 kHz
F
SCL
(1)
(1)
(1)
(1)