PIC18F26K80-I/SO Microchip Technology, PIC18F26K80-I/SO Datasheet - Page 456

• Manufacturer Part Number: PIC18F26K80-I/SO
• Description: MCU PIC 64KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K80-I/SO

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: ECAN, I²C, LIN, SPI, UART/USART
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Controller Family/series: PIC18
• Ram Memory Size: 4KB
• Cpu Speed: 16MIPS
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, USART
• Processor Series: PIC18F26K80
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F66K80 FAMILY
27.13 Bit Timing Configuration
The Baud Rate Control registers
BRGCON2, BRGCON3) control the bit timing for the
CAN bus interface. These registers can only be modi-
fied when the PIC18F66K80 family devices are in
Configuration mode.
27.13.1
The BRP bits control the baud rate prescaler. The
SJW<1:0> bits select the synchronization jump width in
terms of multiples of T
27.13.2
The PRSEG bits set the length of the propagation seg-
ment in terms of T
Phase Segment 1 in T
many times the RXCAN pin is sampled. Setting this bit
to a
at T
sample point (which is at the end of Phase Segment 1).
The value of the bus is determined to be the value read
during at least two of the samples. If the SAM bit is set
to a ‘ 0 ’, then the RXCAN pin is sampled only once at
the sample point. The SEG2PHTS bit controls how the
length of Phase Segment 2 is determined. If this bit is
set to a
determined by the SEG2PH bits of BRGCON3. If the
SEG2PHTS bit is set to a ‘ 0 ’, then the length of Phase
Segment 2 is the greater of Phase Segment 1 and the
information processing time (which is fixed at 2 T
the PIC18F66K80 family).
27.13.3
The PHSEG2<2:0> bits set the length (in T
Segment 2 if the SEG2PHTS bit is set to a ‘ 1 ’. If the
SEG2PHTS bit is set to a ‘ 0 ’, then the PHSEG2<2:0>
bits have no effect.
27.14 Error Detection
The CAN protocol provides sophisticated error
detection mechanisms. The following errors can be
detected.
27.14.1
With the Cyclic Redundancy Check (CRC), the trans-
mitter calculates special check bits for the bit
sequence, from the start of a frame until the end of the
data field. This CRC sequence is transmitted in the
CRC field. The receiving node also calculates the CRC
sequence using the same formula and performs a
comparison to the received sequence. If a mismatch is
detected, a CRC error has occurred and an error frame
is generated. The message is repeated.
DS39977C-page 456
Q
‘
1
/2 before the sample point and once at the normal
’
causes the bus to be sampled three times: twice
Registers
‘
1
’
, then the length of Phase Segment 2 is
BRGCON1
BRGCON2
BRGCON3
CRC ERROR
Q
. The SEG1PH bits set the length of
Q
.
Q
. The SAM bit controls how
(BRGCON1,
Q
) of Phase
Q
Preliminary
for
communication. During this state, messages can neither
27.14.2
In the Acknowledge field of a message, the transmitter
checks if the Acknowledge slot (which was sent out as
a recessive bit) contains a dominant bit. If not, no other
node has received the frame correctly. An Acknowl-
edge error has occurred, an error frame is generated
and the message will have to be repeated.
27.14.3
If a node detects a dominant bit in one of the four seg-
ments, including End-of-Frame (EOF), interframe
space, Acknowledge delimiter or CRC delimiter, then a
form error has occurred and an error frame is
generated. The message is repeated.
27.14.4
A bit error occurs if a transmitter sends a dominant bit
and detects a recessive bit, or if it sends a recessive bit
and detects a dominant bit, when monitoring the actual
bus level and comparing it to the just transmitted bit. In
the case where the transmitter sends a recessive bit
and a dominant bit is detected during the arbitration
field and the Acknowledge slot, no bit error is
generated because normal arbitration is occurring.
27.14.5
lf, between the Start-of-Frame (SOF) and the CRC
delimiter, six consecutive bits with the same polarity are
detected, the bit stuffing rule has been violated. A stuff
bit error occurs and an error frame is generated. The
message is repeated.
27.14.6
Detected errors are made public to all other nodes via
error frames. The transmission of the erroneous mes-
sage is aborted and the frame is repeated as soon as
possible. Furthermore, each CAN node is in one of the
three error states; “error-active”, “error-passive” or
“bus-off”, according to the value of the internal error
counters. The error-active state is the usual state
where the bus node can transmit messages and acti-
vate error frames (made of dominant bits) without any
restrictions. In the error-passive state, messages and
passive error frames (made of recessive bits) may be
transmitted. The bus-off state makes it temporarily
impossible for the node to participate in the bus
be received nor transmitted.
27.14.7
The PIC18F66K80 family devices contain two error
counters: the Receive Error Counter (RXERRCNT) and
the Transmit Error Counter (TXERRCNT). The values of
both counters can be read by the MCU. These counters
are incremented or decremented in accordance with the
CAN bus specification.
ACKNOWLEDGE ERROR
FORM ERROR
BIT ERROR
STUFF BIT ERROR
ERROR STATES
ERROR MODES AND ERROR
COUNTERS
 2011 Microchip Technology Inc.