MT47H256M4BT-5E:A TR Micron Technology Inc, MT47H256M4BT-5E:A TR Datasheet - Page 102

• Manufacturer Part Number: MT47H256M4BT-5E:A TR
• Description: IC DDR2 SDRAM 1GBIT 5NS 92FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H256M4BT-5E:A TR

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 92-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1206-1

Table 42: WRITE Using Concurrent Auto Precharge
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
WRITE with auto precharge
From Command
(Bank n)
the WRITE diagrams show the nominal case, and where the two extreme cases (
[MIN] and
(page 103) shows the nominal case and the extremes of
tion of a burst, assuming no other commands have been initiated, the DQ will remain
High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide continuous flow of input data. The first data element from the new burst is ap-
plied after the last element of a completed burst. The new WRITE command should be
issued x cycles after the first WRITE command, where x equals BL/2.
Figure 58 (page 104) shows concatenated bursts of BL = 4 and how full-speed random
write accesses within a page or pages can be performed. An example of nonconsecutive
WRITEs is shown in Figure 59 (page 104). DDR2 SDRAM supports concurrent auto pre-
charge options, as shown in Table 42.
DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4
operation. Once the BL = 4 WRITE command is registered, it must be allowed to com-
plete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto
precharge disabled) might be interrupted and truncated only by another WRITE burst
as long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architec-
ture of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or
truncated with any command except another WRITE command, as shown in Figure 60
(page 105).
Data for any WRITE burst may be followed by a subsequent READ command. To follow
a WRITE,
cycles required to meet
WRITE burst may be followed by a subsequent PRECHARGE command.
met, as shown in Figure 62 (page 107).
less of the data mask condition.
WRITE or WRITE with auto precharge
READ or READ with auto precharge
t
PRECHARGE or ACTIVATE
WTR should be met, as shown in Figure 61 (page 106). The number of clock
t
DQSS [MAX]) might not be intuitive, they have also been included. Figure 57
To Command
(Bank m)
t
WTR is either 2 or
102
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
WR starts at the end of the data burst, regard-
t
WTR/
(with Concurrent Auto Precharge)
1Gb: x4, x8, x16 DDR2 SDRAM
t
CK, whichever is greater. Data for any
(CL - 1) + (BL/2) +
Minimum Delay
t
DQSS for BL = 4. Upon comple-
(BL/2)
1
© 2004 Micron Technology, Inc. All rights reserved.
t
WTR
t
WR must be
WRITE
t
DQSS
Units
t
t
t
CK
CK
CK