MT47H256M4BT-5E:A TR Micron Technology Inc, MT47H256M4BT-5E:A TR Datasheet - Page 113

IC DDR2 SDRAM 1GBIT 5NS 92FBGA

MT47H256M4BT-5E:A TR

Manufacturer Part Number
MT47H256M4BT-5E:A TR
Description
IC DDR2 SDRAM 1GBIT 5NS 92FBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT47H256M4BT-5E:A TR

Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (256M x 4)
Speed
5ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
92-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1206-1
SELF REFRESH
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
The SELF REFRESH command is initiated when CKE is LOW. The differential clock
should remain stable and meet
refresh mode. The procedure for exiting self refresh requires a sequence of commands.
First, the differential clock must be stable and meet
prior to CKE going back to HIGH. Once CKE is HIGH (
with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com-
mands issued for
ments is used to apply NOP or DESELECT commands for 200 clock cycles before
applying any other command.
t
XSNR. A simple algorithm for meeting both refresh and DLL require-
113
t
CKE specifications at least 1 ×
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
t
CK specifications at least 1 ×
t
CKE [MIN] has been satisfied
© 2004 Micron Technology, Inc. All rights reserved.
t
CK after entering self
SELF REFRESH
t
CK

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