MT47H256M4BT-5E:A TR Micron Technology Inc, MT47H256M4BT-5E:A TR Datasheet - Page 69

• Manufacturer Part Number: MT47H256M4BT-5E:A TR
• Description: IC DDR2 SDRAM 1GBIT 5NS 92FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H256M4BT-5E:A TR

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 92-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1206-1

Table 37: Truth Table – Current State Bank n – Command to Bank n
Notes: 1–6 apply to the entire table
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Current
State
Any
Idle
Row active
Read (auto
precharge
disabled)
Write
(auto pre-
charge disa-
bled)
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
Notes:
RAS#
X
H
H
H
H
H
H
H
L
L
L
L
L
L
6. Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD
7. SELF REFRESH exit is asynchronous.
8. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 48
9. The power-down mode does not perform any REFRESH operations. The duration of power-
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after
2. This table is bank-specific, except where noted (the current state is for a specific bank
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank.
CAS#
MODE command selects which mode register is programmed.
(page 94) and Figure 60 (page 105) for other restrictions and details.
down is limited by the refresh requirements outlined in the AC parametric section.
met (if the previous state was self refresh).
and the commands shown are those allowed to be issued to that bank when in that
state). Exceptions are covered in the notes below.
Issue DESELECT or NOP commands, or allowable commands to the other bank, on any
clock edge occurring during these states. Allowable commands to the other bank are
determined by its current state and this table, and according to Table 38 (page 71).
Idle:
Row
active:
Read: A READ burst has been initiated, with auto precharge disabled and has not yet
Write: A WRITE burst has been initiated with auto precharge disabled and has not yet
X
H
H
H
H
H
L
L
L
L
L
L
L
L
The bank has been precharged,
plete.
A row in the bank has been activated, and
accesses and no register accesses are in progress.
terminated.
terminated.
WE#
X
H
H
H
H
H
H
L
L
L
L
L
L
L
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVATE (select and activate row)
REFRESH
LOAD MODE
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (start PRECHARGE)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (start PRECHARGE)
69
Command/Action
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RP has been met, and any READ burst is com-
1Gb: x4, x8, x16 DDR2 SDRAM
t
RCD has been met. No data bursts/
© 2004 Micron Technology, Inc. All rights reserved.
t
XSNR has been
Commands
Notes
8, 10
7
7
8
8
9
8
9
8
8
9