MT47H256M4BT-5E:A TR Micron Technology Inc, MT47H256M4BT-5E:A TR Datasheet - Page 70

• Manufacturer Part Number: MT47H256M4BT-5E:A TR
• Description: IC DDR2 SDRAM 1GBIT 5NS 92FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H256M4BT-5E:A TR

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 92-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1206-1

PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
10. A WRITE command may be applied after the completion of the READ burst.
5. The following states must not be interrupted by any executable command (DESELECT or
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle and bursts are not in progress.
8. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
9. May or may not be bank-specific; if multiple banks are to be precharged, each must be
NOP commands must be applied on each positive clock edge during these states):
auto precharge enabled and READs or WRITEs with auto precharge disabled.
in a valid state for precharging.
Precharge:
Read with au-
to precharge
enabled:
Row activate: Starts with registration of an ACTIVATE command and ends when
Write with au-
to precharge
enabled:
Refresh:
Accessing
mode
register:
Precharge
all:
Starts with registration of a REFRESH command and ends when
met. After
Starts with registration of the LOAD MODE command and ends when
t
all banks idle state.
Starts with registration of a PRECHARGE ALL command and ends when
t
MRD has been met. After
RP is met. After
Starts with registration of a PRECHARGE command and ends when
is met. After
Starts with registration of a READ command with auto precharge ena-
bled and ends when
be in the idle state.
t
Starts with registration of a WRITE command with auto precharge ena-
bled and ends when
be in the idle state.
RCD is met. After
t
70
RFC is met, the DDR2 SDRAM will be in the all banks idle state.
t
RP is met, the bank will be in the idle state.
t
RP is met, all banks will be in the idle state.
t
RCD is met, the bank will be in the row active state.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
RP has been met. After
RP has been met. After
t
MRD is met, the DDR2 SDRAM will be in the
1Gb: x4, x8, x16 DDR2 SDRAM
© 2004 Micron Technology, Inc. All rights reserved.
t
t
RP is met, the bank will
RP is met, the bank will
Commands
t
RFC is
t
RP