MT47H256M4BT-5E:A TR Micron Technology Inc, MT47H256M4BT-5E:A TR Datasheet - Page 38

• Manufacturer Part Number: MT47H256M4BT-5E:A TR
• Description: IC DDR2 SDRAM 1GBIT 5NS 92FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H256M4BT-5E:A TR

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (256M x 4)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 92-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1206-1

PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Notes:
10. MIN (
11.
12. The period jitter (
13. The half-period jitter (
14. The cycle-to-cycle jitter (
15. The cumulative jitter error (
16. JEDEC specifies using
17. This parameter is not referenced to a specific voltage level but is specified when the de-
1. All voltages are referenced to V
2. Tests for AC timing, I
3. Outputs measured with equivalent load (see Figure 15 (page 47)).
4. AC timing and I
5. The AC and DC input level specifications are as defined in the SSTL_18 standard (that is,
6. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured differentially).
7. Operating frequency is only allowed to change during self refresh mode (see Figure 78
8. The clock’s
9. Spread spectrum is not included in the jitter specification values. However, the input
nominal reference/supply voltage levels, but the related specifications and the opera-
tion of the device are warranted for the full voltage range specified. ODT is disabled for
all measurements that are not ODT-specific.
and parameter specifications are guaranteed for the specified AC input levels under nor-
mal use conditions. The slew rate for the input signals used to test the device is 1.0 V/ns
for signals in the range between V
require the timing parameters to be derated as specified.
the receiver will effectively switch as a result of the signal crossing the AC input level
and will remain in that state as long as the signal does not ring back above [below] the
DC input LOW [HIGH] level).
(page 122)), precharge power-down mode, or system reset condition (see Reset
(page 123)). SSC allows for small deviations in operating frequency, provided the SSC
guidelines are satisfied.
t
clock jitter). Input clock jitter is allowed provided it does not exceed values specified.
Also, the jitter must be of a random Gaussian distribution in nature.
clock can accommodate spread spectrum at a sweep rate in the range 8–60 kHz with an
additional one percent
rate below
HIGH time driven to the device. The clock’s half period must also be of a Gaussian distri-
bution;
without duty cycle jitter.
tive CK falling edges.
that the absolute half period limits (
t
thus,
or nominal clock allowed in either the positive or negative direction. JEDEC specifies
tighter jitter numbers during DLL locking time. During DLL lock time, the jitter values
should be 20 percent less those than noted in the table (DLL locked).
of clock; however, the two cumulatively can not exceed
to the next. JEDEC specifies tighter jitter numbers during DLL locking time. During DLL
lock time, the jitter values should be 20 percent less than those noted in the table (DLL
locked).
of clock time allowed to consecutively accumulate away from the average clock over
any number of clock cycles.
19 and 48). Micron requires less derating by allowing
vice output is no longer driving (
CK (AVG) MIN is the smallest clock rate allowed (except for a deviation due to allowed
HP (MIN) is the lesser of
t
t
CL,
HP (MIN) ≥ the lesser of
t
CH (AVG) and
t
CH) refers to the smaller of the actual clock LOW time and the actual clock
t
t
CK (AVG) is the average clock over any 200 consecutive clocks and
CK (AVG) MIN or above
DD
t
JITper) is the maximum deviation in the clock period from the average
tests may use a V
DD
t
t
ERR
CH limits may be exceeded if the duty cycle jitter is small enough
t
t
JITdty) applies to either the high pulse of clock or the low pulse
, and electrical AC and DC characteristics may be conducted at
t
CL (AVG) must be met with or without clock jitter and with or
CK (AVG); however, the spread spectrum may not use a clock
t
JITcc) is the amount the clock period can deviate from one cycle
t
t
CL and
CH (AVG) and
38
6–10per
t
ERR
t
CL (ABS) MIN and
SS
nper
when derating clock-related output timing (see notes
t
t
.
RPST) or beginning to drive (
CH actually applied to the device CK and CK# inputs;
IL(AC)
IL
), where n is 2, 3, 4, 5, 6–10, or 11–50 is the amount
t
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
CK (AVG) MAX.
-to-V
CH [ABS],
and V
t
CL (AVG) are the average of any 200 consecu-
IH
swing of up to 1.0V in the test environment,
1Gb: x4, x8, x16 DDR2 SDRAM
IH(AC)
t
CL [ABS]) are not violated.
t
CH (ABS) MIN.
. Slew rates other than 1.0 V/ns may
t
ERR
t
JITper.
5per
© 2004 Micron Technology, Inc. All rights reserved.
to be used.
t
RPRE).