LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet
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UM10360 LPC17xx User manual Rev. 2 — 19 August 2010 Document information Info Content Keywords LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1763, LPC1759, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller Abstract LPC17xx user ...
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... NXP Semiconductors Revision history Rev Date Description 2 20100819 LPC17xx user manual revision. Modifications: • UART0/1/2/3: FIFOLVL register removed. • ADC: reset value of the ADCTRM register changed to 0xF00 • Timer0/1/2/3: Description of DMA operation updated. • USB Device: Corrected error in the USBCmdCode register (0x01 = write, 0x02 = read) (Table 220) ...
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UM10360 Chapter 1: LPC17xx Introductory information Rev. 2 — 19 August 2010 1.1 Introduction The LPC17xx is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation. The ARM Cortex- ...
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... NXP Semiconductors 1.2 Features Refer to Section 1.4.1 • ARM Cortex-M3 processor, running at frequencies 120 MHz on high speed versions (LPC1769 and LPC1759 100 MHz on other versions. A Memory Protection Unit (MPU) supporting eight regions is included. • ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). ...
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... NXP Semiconductors 2 – (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I 3-wire data transmit and receive or 4-wire combined transmit and receive connections, as well as master clock output. • Other peripherals: – 70 (100 pin package (80-pin package) General Purpose I/O (GPIO) pins with configurable pull-up/down resistors, open drain mode, and repeater mode ...
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... NXP Semiconductors • Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, PORT0/2 pin interrupt, and NMI). • Each peripheral has its own clock divider for further power savings. ...
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... NXP Semiconductors 1.4 Ordering information Table 1. Ordering information Type number Package Name Description LPC1769FBD100 LPC1768FBD100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm LQFP100 LPC1767FBD100 LPC1766FBD100 LPC1765FBD100 LPC1764FBD100 LPC1763FBD100 LPC1768FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 0.7 mm SOT926-1 ...
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... NXP Semiconductors 1.5 Simplified block diagram Trace Port High Speed GPIO APB slave group 0 SSP1 UARTs 0 & 1 CAN 1 & & 1 SPI0 Capture/Compare Timers 0 & 1 Watchdog Timer PWM1 12-bit ADC Pin Connect Block GPIO Interrupt Ctl 32 kHz Real Time Clock oscillator 20 bytes of backup ...
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... NXP Semiconductors 1.6 Architectural overview The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and D-code buses which are faster and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices ...
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... NXP Semiconductors Debug related options: • A JTAG debug interface is included. • Serial Wire Debug is included. Serial Wire Debug allows debug operations using only 2 wires, simple trace functions can be added with a third wire. • The Embedded Trace Macrocell (ETM) is included. The ETM provides instruction trace capabilities. • ...
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... NXP Semiconductors 1.10 Block diagram JTAG interface Debug Port TEST/DEBUG INTERFACE ARM Cortex-M3 I-code D-code System bus bus bus Multilayer AHB Matrix APB slave group 0 SSP1 UARTs 0 & 1 CAN 1 & & 1 SPI0 Capture/compare timers 0 & 1 Watchdog timer PWM1 12-bit ADC Pin connect block ...
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UM10360 Chapter 2: LPC17xx Memory map Rev. 2 — 19 August 2010 2.1 Memory map and peripheral addressing The ARM Cortex-M3 processor has a single 4 GB address space. The following table shows how this space is used on the ...
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APB1 peripherals 0x4010 0000 31 system control 0x400F C000 reserved 0x400C 0000 15 QEI 0x400B C000 14 motor control PWM 0x400B 8000 13 reserved 0x400B 4000 12 repetitive interrupt ...
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... NXP Semiconductors Figure 3 and peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 megabyte in size and is divided to allow for peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral. ...
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... NXP Semiconductors Table 5. APB1 peripheral 2.4 Memory re-mapping The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the Cortex-M3. Refer to Cortex-M3 User Guide appended to this manual for details of the Vector Table Offset feature ...
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... NXP Semiconductors For these areas, both attempted data access and instruction fetch generate an exception. In addition, a Bus Fault exception is generated for any instruction fetch that maps to an AHB or APB peripheral address. Within the address space of an existing APB peripheral, an exception is not generated in response to an access to an undefined address ...
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UM10360 Chapter 3: LPC17xx System control Rev. 2 — 19 August 2010 3.1 Introduction The system control block includes several system features and control registers for a number of functions that are not related to specific peripheral devices. These include: ...
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... NXP Semiconductors 3.3 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. Table 7. Name External Interrupts EXTINT EXTMODE EXTPOLAR Reset RSID Syscon Miscellaneous Registers SCS 3.4 Reset Reset has 4 sources on the LPC17xx: the RESET pin, Watchdog Reset, Power On Reset (POR), and Brown Out Detect (BOD) ...
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... NXP Semiconductors external reset watchdog reset POR BOD power-down EINT0 wake-up EINT1 wake-up EINT2 wake-up EINT3 wake-up RTC wake-up BOD wake-up Ethernet MAC wake-up USB need_clk wake-up CAN wake-up GPIO0 port wake-up GPIO2 port wake-up Fig 4. Reset block diagram including the wake-up timer On the assertion of a reset source external to the Cortex-M3 CPU (POR, BOD reset, External reset, and Watchdog reset), the IRC starts up ...
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... NXP Semiconductors IRC status RESET V DD(REG)(3V3) GND supply ramp-up time processor status Fig 5. Example of start-up after reset UM10360 User manual IRC IRC starts stable valid threshold 60 μs 1 μs; IRC stability count 7 μs 181 μs flash read starts All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 3.4.1 Reset Source Identification Register (RSID - 0x400F C180) This register contains one bit for each source of Reset. Writing any of these bits clears the corresponding read-side bit to 0. The interactions among the four sources are described below. Table 8. Bit Symbol Description ...
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... NXP Semiconductors 3.5 Brown-out detection The LPC17xx includes a Brown-Out Detector (BOD) that provides 2-stage monitoring of the voltage on the V (typically 2.2 V under nominal room temperature conditions), the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt ...
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... NXP Semiconductors 3.6 External interrupt inputs TheLPC17xx includes four External Interrupt Inputs as selectable pin functions. The logic of an individual external interrupt is represented in have the ability to wake up the CPU from Power-down mode. Refer to “Wake-up from Reduced Power Modes” GLITCH EINTi pin ...
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... NXP Semiconductors 3.6.1 Register description The external interrupt function has four registers associated with it. The EXTINT register contains the interrupt flags. The EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters. Table 9. Name EXTINT EXTMODE EXTPOLAR The External Interrupt Polarity Register controls [1] Reset Value reflects the data stored in used bits only ...
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... NXP Semiconductors Table 10. Bit Symbol Description 0 EINT0 1 EINT1 2 EINT2 3 EINT3 31:4 - [1] Example: corresponding pin, this bit can not be cleared; this bit can be cleared only when signal on the pin becomes high. 3.6.3 External Interrupt Mode register (EXTMODE - 0x400F C148) The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins ...
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... NXP Semiconductors Table 11. Bit Symbol 0 EXTMODE0 1 EXTMODE1 2 EXTMODE2 3 EXTMODE3 31:4 - 3.6.4 External Interrupt Polarity register (EXTPOLAR - 0x400F C14C) In level-sensitive mode, the bits in this register select whether the corresponding pin is high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or falling-edge sensitive. Only pins that are selected for the EINT function Only pins that are ...
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... NXP Semiconductors Table 12. Bit Symbol 3 EXTPOLAR3 0 31:4 - UM10360 User manual External Interrupt Polarity register (EXTPOLAR - address 0x400F C14C) bit description Value Description EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3). 1 EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3). - Reserved, user software should not write ones to reserved bits ...
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... NXP Semiconductors 3.7 Other system controls and status flags Some aspects of controlling LPC17xx operation that do not fit into peripheral or other registers are grouped here. 3.7.1 System Controls and Status register (SCS - 0x400F C1A0) The SCS register contains several control/status bits related to the main oscillator. Since chip operation always begins using the Internal RC Oscillator, and the main oscillator may not be used at all in some applications, it will only be started by software request ...
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UM10360 Chapter 4: LPC17xx Clocking and power control Rev. 2 — 19 August 2010 4.1 Summary of clocking and power control functions This section describes the generation of the various clocks needed by the LPC17xx and options of clock source ...
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... NXP Semiconductors 4.2 Register description All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function. Table 14. Name Clock source selection CLKSRCSEL Phase Locked Loop (PLL0, Main PLL) PLL0CON PLL0CFG PLL0STAT PLL0FEED Phase Locked Loop (PLL1, USB PLL) ...
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... NXP Semiconductors 4.3 Oscillators The LPC17xx includes three independent oscillators. These are the Main Oscillator, the Internal RC Oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. This can be seen in Following Reset, the LPC17xx will operate from the Internal RC Oscillator until switched by software ...
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... NXP Semiconductors LPC17xx XTAL1 XTAL2 C C Clock a) Fig 8. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external crystal model used for C X1 Table 15. Fundamental oscillation frequency F 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz 15 MHz - 20 MHz Table 16. Fundamental oscillation frequency F ...
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... NXP Semiconductors point, software can control switching to the main oscillator as a clock source. Prior to starting the main oscillator, a frequency range must be selected by configuring the OSCRANGE bit in the SCS register. 4.3.3 RTC oscillator The RTC oscillator provides clock to the RTC and a 32 kHz clock output that can be used as the clock source for PLL0 and CPU and/or the watchdog timer ...
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... NXP Semiconductors 4.4 Clock source selection multiplexer Several clock sources may be chosen to drive PLL0 and ultimately the CPU and on-chip peripheral devices. The clock sources available are the main oscillator, the RTC oscillator, and the Internal RC oscillator. The clock source selection can only be changed safely when PLL0 is not connected. For a detailed description of how to change the clock source in a system using PLL0 see Section 4.5.13 “ ...
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... NXP Semiconductors 4.5 PLL0 (Phase Locked Loop 0) PLL0 accepts an input clock frequency in the range of 32 kHz to 50 MHz. The clock source is selected in the CLKSRCSEL register (see multiplied high frequency, then divided down to provide the actual clock used by the CPU, peripherals, and optionally the USB subsystem. Note that the USB subsystem ...
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... NXP Semiconductors 4.5.2 PLL0 register description PLL0 is controlled by the registers shown in Warning: Improper setting of PLL0 values may result in incorrect operation of the device! Table 18. Name PLL0CON PLL0CFG PLL0STAT PLL0FEED PLL0 Feed Register. This register enables [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. ...
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... NXP Semiconductors output clock. Changes to the PLL0CON register do not take effect until a correct PLL0 feed sequence has been given (see 0x400F C08C)”). Table 19. Bit Symbol 0 PLLE0 1 PLLC0 31:2 - PLL0 must be set up, enabled, and Lock established before it may be used as a clock source ...
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... NXP Semiconductors Table 21. Multiplier (M) 4272 4395 4578 4725 4807 5127 5188 5400 5493 5859 6042 6075 6104 6409 6592 6750 6836 6866 6958 7050 7324 7425 7690 7813 7935 8057 8100 8545 8789 9155 9613 10254 10376 10986 11719 UM10360 User manual ...
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... NXP Semiconductors 4.5.5 PLL0 Status register (PLL0STAT - 0x400F C088) The read-only PLL0STAT register provides the actual PLL0 parameters that are in effect at the time it is read, as well as PLL0 status. PLL0STAT may disagree with values found in PLL0CON and PLL0CFG because changes to those registers do not take effect until a ...
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... NXP Semiconductors 4.5.7 PLL0 Modes The combinations of PLLE0 and PLLC0 are shown in Table 23. PLLC0 PLLE0 PLL Function 4.5.8 PLL0 Feed register (PLL0FEED - 0x400F C08C) A correct feed sequence must be written to the PLL0FEED register in order for changes to the PLL0CON and PLL0CFG registers to take effect. The feed sequence is: 1 ...
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... NXP Semiconductors Table 25. Parameter CCO REF The PLL0 output frequency (when PLL0 is both active and connected) is given by × M × CCO PLL inputs and settings must meet the following: • the range of 32 kHz to 50 MHz. IN • the range of 275 MHz to 550 MHz. ...
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... NXP Semiconductors Table 26. 4272 5127 6042 6750 7324 8057 9613 12085 13733 15381 16479 19775 21973 4.5.11 Procedure for determining PLL0 settings PLL0 parameter determination can be simplified by using a spreadsheet available from NXP. To determine PLL0 parameters by hand, the following general procedure may be used: 1 ...
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... NXP Semiconductors 4.5.12 Examples of PLL0 settings The following table gives a summary of examples that illustrate selecting PLL0 values based on different system requirements. Table 27. Example Example 1 Assumptions: • The USB interface will not be used in the application, or will be clocked by PLL1. • The desired CPU rate is 100 MHz. ...
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... NXP Semiconductors Example 2 Assumptions: • The USB interface will be used in the application and will be clocked from PLL0. • The desired CPU rate is 60 MHz. • An external 4 MHz crystal or clock source will be used as the system clock source. This clock source could be the Internal RC oscillator (IRC). ...
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... NXP Semiconductors Example 3 Assumptions: • The USB interface will not be used in the application, or will be clocked by PLL1. • The desired CPU rate is 72 MHz • The 32.768 kHz RTC clock source will be used as the system clock source Calculations CCO The smallest integer multiple of the desired CPU clock rate that is within the PLL0 operating range is 288 MHz (4 × ...
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... NXP Semiconductors 4.5.13 PLL0 setup sequence The following sequence must be followed step by step in order to have PLL0 initialized and running: 1. Disconnect PLL0 with one feed sequence if PLL0 is already connected. 2. Disable PLL0 with one feed sequence. 3. Change the CPU Clock Divider setting to speed up operation without PLL0, if desired. ...
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... NXP Semiconductors 4.6 PLL1 (Phase Locked Loop 1) PLL1 receives its clock input from the main oscillator only and can be used to provide a fixed 48 MHz clock only to the USB subsystem. This is an option in addition to the possibility of generating the USB clock from PLL0. PLL1 is disabled and powered off on reset. If PLL1 is left disabled, the USB clock can be supplied by PLL0 if everything is set up to provide 48 MHz through that route ...
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... NXP Semiconductors Table 29. Name PLL1CFG PLL1STAT PLL1FEED [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. PLOCK PLLSTAT[10] PLL input clock Phase Detector Divide by M MSEL PLLSTAT[4:0] Fig 10. PLL1 block diagram 4.6.2 PLL1 Control register (PLL1CON - 0x400F C0A0) The PLL1CON register contains the bits that enable and connect PLL1 ...
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... NXP Semiconductors Table 30. Bit Symbol 0 PLLE1 1 PLLC1 31:2 - PLL1 must be set up, enabled, and lock established before it may be used as a clock source for the USB subsystem. The hardware does not insure that the PLL is locked before it is connected nor does it automatically disconnect the PLL if lock is lost during operation ...
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... NXP Semiconductors Table 32. Bit Symbol 4:0 MSEL1 6:5 PSEL1 PLLE1_STAT Read-back for the PLL1 Enable bit. When one, PLL1 is currently 9 PLLC1_STAT Read-back for the PLL1 Connect bit. When PLLC and PLLE are 10 PLOCK1 31:11 - 4.6.4.1 PLL1 modes The combinations of PLLE1 and PLLC1 are shown in Table 33 ...
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... NXP Semiconductors 4.6.6 PLL1 Feed register (PLL1FEED - 0x400F C0AC) A correct feed sequence must be written to the PLL1FEED register in order for changes to the PLL1CON and PLL1CFG registers to take effect. The feed sequence is: 1. Write the value 0xAA to PLL1FEED. 2. Write the value 0x55 to PLL1FEED. ...
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... NXP Semiconductors 4.6.8 PLL1 frequency calculation The PLL1 equations use the following parameters: Table 35. Element F OSC F CCO USBCLK M P The PLL1 output frequency (when the PLL is both active and connected) is given by: USBCLK = M × F The CCO frequency can be computed as: = USBCLK × 2 × ...
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... NXP Semiconductors Table 36. Values allowed for using PLL1 with USB are highlighted. PSEL1 Bits (PLL1CFG bits [6:5 Table 37. Values allowed for using PLL1 with USB are highlighted. MSEL1 Bits (PLL1CFG bits [4:0]) 00000 00001 00010 00011 ... 11110 11111 UM10360 User manual ...
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... NXP Semiconductors 4.7 Clock dividers The output of the PLL0 must be divided down for use by the CPU and the USB subsystem (if used with PLL0, see frequency can be determined independently from the USB subsystem, which always requires 48 MHz with a 50% duty cycle for proper operation. ...
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... NXP Semiconductors Table 38. Bit Symbol 7:0 CCLKSEL 31:8 - The CCLK is derived from the PLL0 output signal, divided by CCLKSEL + 1. Having CCLKSEL = 2 results in CCLK being one third of the PLL0 output, CCLKSEL = 3 results in CCLK being one quarter of the PLL0 output, etc. 4.7.2 USB Clock Configuration register (USBCLKCFG - 0x400F C108) This register is used only if the USB PLL (PLL1) is not connected (via the PLLC1 bit in PLL1CON) ...
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... NXP Semiconductors Table 39. Bit Symbol 3:0 USBSEL 31:4 - 4.7.3 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 - 0x400F C1A8 and PCLKSEL1 - 0x400F C1AC) A pair of bits in a Peripheral Clock Selection register controls the rate of the clock signal that will be supplied to the corresponding peripheral as specified in Table 42 ...
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... NXP Semiconductors Table 41. Bit Symbol 1:0 PCLK_QEI 3:2 PCLK_GPIOINT 5:4 PCLK_PCB 7:6 PCLK_I2C1 9:8 - 11:10 PCLK_SSP0 13:12 PCLK_TIMER2 15:14 PCLK_TIMER3 17:16 PCLK_UART2 19:18 PCLK_UART3 21:20 PCLK_I2C2 23:22 PCLK_I2S 25:24 - 27:26 PCLK_RIT 29:28 PCLK_SYSCON 31:30 PCLK_MC Table 42. PCLKSEL0 and PCLKSEL1 individual peripheral’s clock ...
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... NXP Semiconductors 4.8 Power control The LPC17xx supports a variety of power control features: Sleep mode, Deep Sleep mode, Power-down mode, and Deep Power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, re-configuring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements ...
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... NXP Semiconductors When the chip enters the Deep Sleep mode, the main oscillator is powered down, nearly all clocks are stopped, and the DSFLAG bit in PCON is set, see remains running and can be configured to drive the Watchdog Timer, allowing the Watchdog to wake up the CPU. The 32 kHz RTC oscillator is not stopped and RTC interrupts may be used as a wake-up source ...
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... NXP Semiconductors 4.8.4 Deep Power-down mode In Deep Power-down mode, power is shut off to the entire chip with the exception of the Real-Time Clock, the RESET pin, the WIC, and the RTC backup registers. Entry to Deep Power-down mode causes the DPDFLAG bit in PCON to be set, see To optimize power conservation, the user has the additional option of turning off or retaining power to the 32 kHz oscillator ...
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... NXP Semiconductors 4.8.7 Power Mode Control register (PCON - 0x400F C0C0) Controls for some reduced power modes and other power related controls are contained in the PCON register, as described in Table 44. Bit Symbol 0 PM0 1 PM1 2 BODRPM Brown-Out Reduced Power Mode. When BODRPM is 1, the ...
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... NXP Semiconductors 4.8.7.1 Encoding of Reduced Power Modes The PM1and PM0 bits in PCON allow entering reduced power modes as needed. The encoding of these bits allows backward compatibility with devices that previously only supported Sleep and Power-down modes. three reduced power modes supported by the LPC17xx. ...
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... NXP Semiconductors Some peripherals, particularly those that include analog functions, may consume power that is not clock dependent. These peripherals may contain a separate disable control that turns off additional circuitry to reduce power. Information on peripheral specific power saving features may be found in the chapter describing that peripheral. ...
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... NXP Semiconductors Table 46. Bit Symbol 27 PCI2S PCGPDMA 30 PCENET 31 PCUSB Note that the DAC peripheral does not have a control bit in PCONP. To enable the DAC, its output must be selected to appear on the related pin, P0.26, by configuring the PINSEL1 register. See 0x4002 C004)”. 4.8.10 Power control usage notes After every reset, the PCONP register contains the value that enables selected interfaces and peripherals controlled by the PCONP to be enabled ...
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... NXP Semiconductors 4.9 Wake-up timer The LPC17xx begins operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to begin quickly. If the main oscillator or one or both PLLs are needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source ...
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... NXP Semiconductors 4.10 External clock output pin For system test and development purposes, any one of several internal clocks may be brought out on the CLKOUT function available on the P1.27 pin, as shown in Clocks that may be observed via CLKOUT are the CPU clock (cclk), the main oscillator (osc_clk), the internal RC oscillator (irc_osc), the USB clock (usb_clk), and the RTC clock (rtc_clk) ...
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... NXP Semiconductors Table 47. Bit Symbol 7:4 CLKOUTDIV 8 CLKOUT_EN 9 CLKOUT_ACT 31:10 - UM10360 User manual Chapter 4: LPC17xx Clocking and power control Clock Output Configuration register (CLKOUTCFG - 0x400F C1C8) bit description Value Description Integer value to divide the output clock by, minus one. 0000 Clock is divided by 1. ...
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UM10360 Chapter 5: LPC17xx Flash accelerator Rev. 2 — 19 August 2010 5.1 Introduction The flash accelerator block in the LPC17xx allows maximization of the performance of the Cortex-M3 processor when it is running code from flash memory, while also ...
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... NXP Semiconductors 5.2.2 Flash programming Issues Since the flash memory does not allow accesses during programming and erase operations necessary for the flash accelerator to force the CPU to wait if a memory access to a flash address is requested while the flash memory is busy with a programming operation ...
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... NXP Semiconductors 5.4 Flash Accelerator Configuration register (FLASHCFG - 0x400F C000) Configuration bits select the flash access time, as shown in FLASHCFG control internal flash accelerator functions and should not be altered. Following reset, flash accelerator functions are enabled and flash access timing is set to a default value of 4 clocks. ...
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... NXP Semiconductors If a flash instruction fetch and a flash data access from the CPU occur at the same time, the multilayer matrix gives precedence to the data access. This is because a stalled data access always slows down execution, while a stalled instruction fetch often does not. ...
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UM10360 Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC) Rev. 2 — 19 August 2010 6.1 Features • Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3 • Tightly coupled interrupt controller provides low interrupt latency ...
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... NXP Semiconductors Table 50. Connection of interrupt sources to the Vectored Interrupt Controller Interrupt Exception Vector Function ID Number Offset 0 16 0x40 WDT 1 17 0x44 Timer 0x48 Timer 0x4C Timer 0x50 Timer 0x54 UART0 6 22 0x58 UART1 7 23 0x5C UART 0x60 UART 0x64 PWM1 2 10 ...
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... NXP Semiconductors Table 50. Connection of interrupt sources to the Vectored Interrupt Controller Interrupt Exception Vector Function ID Number Offset 14 30 0x78 SSP0 15 31 0x7C SSP 0x80 PLL0 (Main PLL 0x84 RTC 18 34 0x88 External Interrupt 19 35 0x8C External Interrupt 20 36 0x90 External Interrupt 21 37 ...
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... NXP Semiconductors 6.4 Vector table remapping The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register (VTOR) contained in the Cortex-M3. The vector table may be located anywhere within the bottom Cortex-M3 address space ...
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... NXP Semiconductors 6.5 Register description The following table summarizes the registers in the NVIC as implemented in the LPC17xx. The Cortex-M3 User Guide Table 51. NVIC register map Name Description ISER0 to Interrupt Set-Enable Registers. These 2 registers allow enabling ISER1 interrupts and reading back the interrupt enables for specific peripheral functions ...
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... NXP Semiconductors 6.5.1 Interrupt Set-Enable Register 0 register (ISER0 - 0xE000 E100) The ISER0 register allows enabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are enabled via the ISER1 register (Section registers (Section 6.5.3 Table 52. ...
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... NXP Semiconductors 6.5.2 Interrupt Set-Enable Register 1 register (ISER1 - 0xE000 E104) The ISER1 register allows enabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Disabling interrupts is done through the ICER0 and ICER1 registers Table 53. Interrupt Set-Enable Register 1 register (ISER1 - 0xE000 E104) ...
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... NXP Semiconductors 6.5.3 Interrupt Clear-Enable Register 0 (ICER0 - 0xE000 E180) The ICER0 register allows disabling the first 32 peripheral interrupts, or for reading the enabled state of those interrupts. The remaining interrupts are disabled via the ICER1 register (Section registers (Section 6.5.1 Table 54. Interrupt Clear-Enable Register 0 (ICER0 - 0xE000 E180) ...
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... NXP Semiconductors 6.5.4 Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184) The ICER1 register allows disabling the second group of peripheral interrupts, or for reading the enabled state of those interrupts. Enabling interrupts is done through the ISER0 and ISER1 registers Table 55. Interrupt Clear-Enable Register 1 register (ICER1 - 0xE000 E184) ...
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... NXP Semiconductors 6.5.5 Interrupt Set-Pending Register 0 register (ISPR0 - 0xE000 E200) The ISPR0 register allows setting the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. The remaining interrupts can have their pending state set via the ISPR1 register ...
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... NXP Semiconductors 6.5.6 Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204) The ISPR1 register allows setting the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. Clearing the pending state of interrupts is done through the ICPR0 and ICPR1 registers Section 6 ...
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... NXP Semiconductors 6.5.7 Interrupt Clear-Pending Register 0 register (ICPR0 - 0xE000 E280) The ICPR0 register allows clearing the pending state of the first 32 peripheral interrupts, or for reading the pending state of those interrupts. The remaining interrupts can have their pending state cleared via the ICPR1 register ...
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... NXP Semiconductors 6.5.8 Interrupt Clear-Pending Register 1 register (ICPR1 - 0xE000 E284) The ICPR1 register allows clearing the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. Setting the pending state of interrupts is done through the ISPR0 and ISPR1 registers Section 6 ...
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... NXP Semiconductors 6.5.9 Interrupt Active Bit Register 0 (IABR0 - 0xE000 E300) The IABR0 register is a read-only register that allows reading the active state of the first 32 peripheral interrupts. This allows determining which peripherals are asserting an interrupt to the NVIC, and may also be pending if there are enabled. The remaining interrupts can have their active state read via the IABR1 register Table 60 ...
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... NXP Semiconductors 6.5.10 Interrupt Active Bit Register 1 (IABR1 - 0xE000 E304) The IABR1 register is a read-only register that allows reading the active state of the second group of peripheral interrupts. This allows determining which peripherals are asserting an interrupt to the NVIC, and may also be pending if there are enabled. ...
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... NXP Semiconductors 6.5.11 Interrupt Priority Register 0 (IPR0 - 0xE000 E400) The IPR0 register controls the priority of the first 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 62. Interrupt Priority Register 0 (IPR0 - 0xE000 E400) Bit Name Function ...
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... NXP Semiconductors 6.5.14 Interrupt Priority Register 3 (IPR3 - 0xE000 E40C) The IPR3 register controls the priority of the fourth group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 65. Interrupt Priority Register 3 (IPR3 - 0xE000 E40C) Bit ...
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... NXP Semiconductors 6.5.17 Interrupt Priority Register 6 (IPR6 - 0xE000 E418) The IPR6 register controls the priority of the seventh group of 4 peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 68. Interrupt Priority Register 6 (IPR6 - 0xE000 E418) Bit ...
Page 90
... NXP Semiconductors 6.5.20 Software Trigger Interrupt Register (STIR - 0xE000 EF00) The STIR register provides an alternate way for software to generate an interrupt, in addition to using the ISPR registers. This mechanism can only be used to generate peripheral interrupts, not system exceptions. By default, only privileged software can write to the STIR register. Unprivileged software ...
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UM10360 Chapter 7: LPC17xx Pin configuration Rev. 2 — 19 August 2010 7.1 LPC17xx pin configuration Fig 14. LPC176x LQFP100 pin configuration Fig 15. LPC175x LQFP80 pin configuration UM10360 User manual All information provided in this ...
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... NXP Semiconductors Fig 16. Pin configuration TFBGA100 package Table 72. Pin allocation table TFBGA100 package Pin Symbol Pin Symbol Row A 1 TDO/SWO 2 P0[3]/RXD0/AD0[6] 5 P1[10]/ENET_RXD1 6 P1[16]/ENET_MDC 9 P0[7]/I2STX_CLK/ 10 P0[9]/I2STX_SDA/ SCK1/MAT2[1] MOSI1/MAT2[3] Row B 1 TMS/SWDIO 2 RTCK 5 P1[9]/ENET_RXD0 6 P1[17]/ ENET_MDIO 9 P2[0]/PWM1[1]/TXD1 ...
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... NXP Semiconductors Table 72. Pin allocation table TFBGA100 package Pin Symbol Pin Symbol 5 P0[23]/AD0[0]/ 6 P4[29]/TX_MCLK/ I2SRX_CLK/CAP3[0] MAT2[1]/RXD3 9 P2[7]/RD2/RTS1 10 P2[8]/TD2/TXD2 Row F 1 VREFN 2 RTCX1 5 P1[21]/MCABORT/ 6 P0[18]/DCD1/ PWM1[3]/SSEL0 MOSI0/MOSI 9 P0[17]/CTS1/ 10 P0[15]/TXD1/ MISO0/MISO SCK0/SCK Row G ...
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... NXP Semiconductors Table 72. Pin allocation table TFBGA100 package Pin Symbol Pin Symbol Row J 1 P0[28]/SCL0/ 2 P0[27]/SDA0/ USB_SCL USB_SDA 5 P1[22]/MCOB0 USB_PWRD/ MAT1[0] 9 P2[13]/EINT3/ 10 P2[10]/EINT0/NMI I2STX_SDA Row K 1 P3[26]/STCLK MAT0[1]/PWM1[3] 5 P1[23]/MCI1/ 6 P1[26]/MCOB1/ PWM1[4]/MISO0 ...
Page 95
... NXP Semiconductors Table 73. Pin description Symbol LQFP LQFP 100 80 P0[0] to P0[31] P0[0] / RD1 / 46 37 TXD3 / SDA1 P0[1] / TD1 / 47 38 RXD3 / SCL1 P0[2] / TXD0 / 98 79 AD0[7] P0[3] / RXD0 / 99 80 AD0[6] P0[ I2SRX_CLK / RD2 / CAP2[0] P0[5] / I2SRX_WS / 80 - TD2 / CAP2[1] P0[ I2SRX_SDA / SSEL1 / MAT2[0] P0[ I2STX_CLK / SCK1 / MAT2[1] ...
Page 96
... NXP Semiconductors Table 73. Pin description …continued Symbol LQFP LQFP 100 80 P0[8] / I2STX_WS / 77 62 MISO1 / MAT2[2] P0[ I2STX_SDA / MOSI1 / MAT2[3] P0[10] / TXD2 / 48 39 SDA2 / MAT3[0] P0[11] / RXD2 / 49 40 SCL2 / MAT3[1] P0[15] / TXD1 / 62 47 SCK0 / SCK P0[16] / RXD1 / 63 48 SSEL0 / SSEL P0[17] / CTS1 / 61 46 ...
Page 97
... NXP Semiconductors Table 73. Pin description …continued Symbol LQFP LQFP 100 80 - P0[20] / DTR1 / 58 SCL1 - P0[21] / RI1 / RD1 57 P0[22] / RTS1 / TD1 56 44 P0[23] / AD0[ I2SRX_CLK / CAP3[0] P0[24] / AD0[ I2SRX_WS / CAP3[1] P0[25] / AD0[ I2SRX_SDA / TXD3 P0[26] / AD0[ AOUT / RXD3 P0[27] / SDA0 / 25 - USB_SDA UM10360 User manual ...
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... NXP Semiconductors Table 73. Pin description …continued Symbol LQFP LQFP 100 80 P0[28] / SCL0 / 24 - USB_SCL P0[29] / USB_D + 29 22 P0[30] / USB_D − P1[0] to P1[31] P1[ ENET_TXD0 P1[ ENET_TXD1 P1[ ENET_TX_EN P1[ ENET_CRS P1[ ENET_RXD0 P1[10 ENET_RXD1 P1[14 ENET_RX_ER P1[15 ENET_REF_CLK P1[16 ENET_MDC - P1[17 ENET_MDIO UM10360 User manual Chapter 7: LPC17xx Pin configuration ...
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... NXP Semiconductors Table 73. Pin description …continued Symbol LQFP LQFP 100 80 P1[18 USB_UP_LED / PWM1[1] / CAP1[0] P1[19] / MCOA0 / 33 26 USB_PPWR / CAP1[1] P1[20] / MCI0 / 34 27 PWM1[2] / SCK0 - P1[21 MCABORT / PWM1[3] / SSEL0 P1[22] / MCOB0 / 36 28 USB_PWRD / MAT1[0] P1[23] / MCI1 / 37 29 PWM1[4] / MISO0 P1[24] / MCI2 / 38 30 ...
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... NXP Semiconductors Table 73. Pin description …continued Symbol LQFP LQFP 100 80 - P1[27] / CLKOUT / 43 USB_OVRCR / CAP0[1] P1[28] / MCOA2 / 44 35 PCAP1[0] / MAT0[0] P1[29] / MCOB2 / 45 36 PCAP1[1] / MAT0[1] P1[30 BUS AD0[4] P1[31] / SCK1 / 20 17 AD0[5] P2[0] to P2[31] P2[0] / PWM1[ TXD1 P2[1] / PWM1[ RXD1 P2[2] / PWM1[3] / ...
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... NXP Semiconductors Table 73. Pin description …continued Symbol LQFP LQFP 100 80 P2[4] / PWM1[ DSR1 / TRACEDATA[1] P2[5] / PWM1[ DTR1 / TRACEDATA[0] P2[6] / PCAP1[ RI1 / TRACECLK P2[7] / RD2 / 66 51 RTS1 P2[8] / TD2 / 65 50 TXD2 / ENET_MDC P2[ USB_CONNECT / RXD2 / ENET_MDIO P2[10] / EINT0 / 53 41 NMI P2[11] / EINT1 / 52 - I2STX_CLK ...
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... NXP Semiconductors Table 73. Pin description …continued Symbol LQFP LQFP 100 80 P2[12] / EINT2 / 51 - I2STX_WS P2[13] / EINT3 / 50 - I2STX_SDA P3[0] to P3[31] - P3[25] / MAT0[ PWM1[2] - P3[26] / STCLK / 26 MAT0[1] / PWM1[3] P4[0] to P4[31] P4[28 RX_MCLK / MAT2[0] / TXD3 P4[29] TX_MCLK / 85 68 MAT2[1] / RXD3 TDO / SWO 1 1 TDI 2 2 TMS / SWDIO ...
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... NXP Semiconductors Table 73. Pin description …continued Symbol LQFP LQFP 100 80 RSTOUT 14 11 RESET 17 14 [1] [1] XTAL1 22 19 [1] [1] XTAL2 23 20 [1] [1] RTCX1 16 13 [1] [1] RTCX2 31, 41, 24, 33, SS 55, 72, 43, 57, [1] 83, 97 66, 78 [1] [ SSA V 28, 54, 21, 42, DD(3V3) [1] 71, 96 56, 77 [1] V 42, 84 34, 67 ...
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UM10360 Chapter 8: LPC17xx Pin connect block Rev. 2 — 19 August 2010 8.1 How to read this chapter Table 74 shows the functions of the PINSEL registers in the LPC17xx. Table 74. Register PINSEL0 PINSEL1 PINSEL2 PINSEL3 PINSEL4 PINSEL5 ...
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... NXP Semiconductors The direction control bit in the GPIO registers is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. Each derivative typically has a different pinout and therefore a different set of functions possible for each pin. Details for a specific derivative may be found in the appropriate data sheet. ...
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... NXP Semiconductors Function of PINMODE in open drain mode Normally the value of PINMODE applies to a pin only when the input mode. When a pin is in the open drain mode, caused the corresponding bit of one of the PINMODE_OD registers, the input mode still does not apply when the pin is outputting a 0. However, when the pin value is 1, PINMODE applies since this state turns off the pin’ ...
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... NXP Semiconductors 8.5 Register description The Pin Control Module contains 11 registers as shown in Table 78. Name PINSEL0 PINSEL1 PINSEL2 PINSEL3 PINSEL4 PINSEL7 PINSEL8 PINSEL9 PINSEL10 PINMODE0 PINMODE1 PINMODE2 PINMODE3 PINMODE4 PINMODE5 PINMODE6 PINMODE7 PINMODE9 PINMODE_OD0 PINMODE_OD1 PINMODE_OD2 PINMODE_OD3 PINMODE_OD4 I2CPADCFG [1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content. ...
Page 108
... NXP Semiconductors 8.5.1 Pin Function Select register 0 (PINSEL0 - 0x4002 C000) The PINSEL0 register controls the functions of the lower half of Port 0. The direction control bit in FIO0DIR register is effective only when the GPIO function is selected for a pin. For other functions, the direction is controlled automatically. ...
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... NXP Semiconductors Table 80. PINSEL1 Pin name Function when 27:26 P0.29 29:28 P0.30 31:30 - [1] Not available on 80-pin package. [2] Pins P027] and P0[28] are open-drain for I 8.5.3 Pin Function Select register 2 (PINSEL2 - 0x4002 C008) The PINSEL2 register controls the functions of the lower half of Port 1, which contains the Ethernet related pins ...
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... NXP Semiconductors Table 82. PINSEL3 Pin name 15:14 P1.23 17:16 P1.24 19:18 P1.25 21:20 P1.26 23:22 P1.27 25:24 P1.28 27:26 P1.29 29:28 P1.30 31:30 P1.31 [1] Not available on 80-pin package. 8.5.5 Pin Function Select Register 4 (PINSEL4 - 0x4002 C010) The PINSEL4 register controls the functions of the lower half of Port 2. The direction control bit in the FIO2DIR register is effective only when the GPIO function is selected for a pin ...
Page 111
... NXP Semiconductors 8.5.6 Pin Function Select Register 7 (PINSEL7 - 0x4002 C01C) The PINSEL7 register controls the functions of the upper half of Port 3. The direction control bit in the FIO3DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. ...
Page 112
... NXP Semiconductors 8.5.9 Pin Mode select register 0 (PINMODE0 - 0x4002 C040) This register controls pull-up/pull-down resistor configuration for Port 0 pins 0 to 15. Table 87. PINMODE0 Symbol 1:0 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 29:24 31:30 [1] Not available on 80-pin package. ...
Page 113
... NXP Semiconductors Table 88. PINMODE1 Symbol 21:20 29:22 31:30 [1] Not available on 80-pin package. [2] The pin mode cannot be selected for pins P0[27] to P0[30]. Pins P0[27] and P0[28] are dedicated I2C open-drain pins without pull-up/down. Pins P0[29] and P0[30] are USB specific pins without configurable pull-up or pull-down resistors ...
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... NXP Semiconductors Table 90. PINMODE3 Symbol 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 [1] Not available on 80-pin package. 8.5.13 Pin Mode select register 4 (PINMODE4 - 0x4002 C050) This register controls pull-up/pull-down resistor configuration for Port 2 pins 0 to 15. For details see Table 91. ...
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... NXP Semiconductors 8.5.14 Pin Mode select register 7 (PINMODE7 - 0x4002 C05C) This register controls pull-up/pull-down resistor configuration for Port 3 pins 16 to 31. For details see Table 92. PINMODE7 Symbol 17:0 19:18 21:20 31:22 [1] Not available on 80-pin package. 8.5.15 Pin Mode select register 9 (PINMODE9 - 0x4002 C064) This register controls pull-up/pull-down resistor configuration for Port 4 pins ...
Page 116
... NXP Semiconductors Table 94. PINMODE _OD0 10 11 14: 28: [1] Not available on 80-pin package. [2] Port 0 pins 27 and 28 should be set up using the I2CPADCFG register if they are used for and 28 of PINMODE_OD0 do not have any affect on these pins, they are special open drain I compatible pins. [3] Port 0 bits 1:0, 11:10, and 20:19 may potentially be used for I should be configured for open drain mode via the related bits in PINMODE_OD0 ...
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... NXP Semiconductors Table 95. PINMODE _OD1 7 13: [1] Not available on 80-pin package. 8.5.18 Open Drain Pin Mode select register 2 (PINMODE_OD2 - 0x4002 C070) This register controls the open drain mode for Port 2 pins. For details see mode select register Table 96. PINMODE _OD2 UM10360 User manual ...
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... NXP Semiconductors Table 96. PINMODE _OD2 31:14 [1] Not available on 80-pin package. 8.5.19 Open Drain Pin Mode select register 3 (PINMODE_OD3 - 0x4002 C074) This register controls the open drain mode for Port 3 pins. For details see mode select register Table 97. PINMODE _OD3 24 31:27 [1] Not available on 80-pin package. ...
Page 119
... NXP Semiconductors Table 98. PINMODE _OD4 28 29 31:30 2 8.5. Pin Configuration register (I2CPADCFG - 0x4002 C07C) The I2CPADCFG register allows configuration of the I order to support various I the 4 bits in I2CPADCFG should be 0, the default value for this register. For Fast Mode Plus, the SDADRV0 and SCLDRV0 bits should be 1. For non-I be desirable to turn off ...
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UM10360 Chapter 9: LPC17xx General Purpose Input/Output (GPIO) Rev. 2 — 19 August 2010 9.1 Basic configuration GPIOs are configured using the following registers: 1. Power: always enabled. 2. Pins: See 3. Wake-up: GPIO ports 0 and 2 can be ...
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... NXP Semiconductors • Registers provide a software view of pending rising edge interrupts, pending falling edge interrupts, and overall pending GPIO interrupts. • GPIO0 and GPIO2 interrupts share the same position in the NVIC with External Interrupt 3. 9.3 Applications • General purpose I/O • ...
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... NXP Semiconductors 9.5 Register description Due to compatibility requirements with the LPC2300 series ARM7-based products, the LPC17xx implements portions of five 32-bit General Purpose I/O ports. Details on a specific GPIO port usage can be found in The registers in GPIO ports. These registers are located on an AHB bus for fast read and write timing. ...
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... NXP Semiconductors Table 102. GPIO interrupt register map Generic Description Name IntEnR GPIO Interrupt Enable for Rising edge. IntEnF GPIO Interrupt Enable for Falling edge. IntStatR GPIO Interrupt Status for Rising edge. IntStatF GPIO Interrupt Status for Falling edge. IntClr GPIO Interrupt Clear. ...
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... NXP Semiconductors Table 104. Fast GPIO port Direction control byte and half-word accessible register Generic Register name FIOxDIR0 FIOxDIR1 FIOxDIR2 FIOxDIR3 FIOxDIRL FIOxDIRU Fast GPIO Port x Direction 9.5.2 GPIO port output Set register FIOxSET (FIO0SET to FIO4SET - 0x2009 C018 to 0x2009 C098) This register is used to produce a HIGH level output at the port pins configured as GPIO in an OUTPUT mode ...
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... NXP Semiconductors Access to a port pin via the FIOxSET register is conditioned by the corresponding bit of the FIOxMASK register (see Table 105. Fast GPIO port output Set register (FIO0SET to FIO4SET - addresses 0x2009 C018 Bit Symbol 31:0 FIO0SET FIO1SET FIO2SET FIO3SET FIO4SET Aside from the 32-bit long and word only accessible FIOxSET register, every fast GPIO ...
Page 126
... NXP Semiconductors 9.5.3 GPIO port output Clear register FIOxCLR (FIO0CLR to FIO4CLR- 0x2009 C01C to 0x2009 C09C) This register is used to produce a LOW level output at port pins configured as GPIO in an OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears the corresponding bit in the FIOxSET register. Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing to FIOxCLR has no effect ...
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... NXP Semiconductors Table 108. Fast GPIO port output Clear byte and half-word accessible register description Generic Register name FIOxCLR3 Fast GPIO Port x output FIOxCLRL Fast GPIO Port x output FIOxCLRU Fast GPIO Port x output 9.5.4 GPIO port Pin value register FIOxPIN (FIO0PIN to FIO4PIN- 0x2009 ...
Page 128
... NXP Semiconductors Only pins masked with zeros in the Mask register (see the current content of the Fast GPIO port pin value register. Table 109. Fast GPIO port Pin value register (FIO0PIN to FIO4PIN- addresses 0x2009 C014 to Bit Symbol 31:0 FIO0VAL FIO1VAL FIO2VAL FIO3VAL ...
Page 129
... NXP Semiconductors Table 110. Fast GPIO port Pin value byte and half-word accessible register description Generic Register name FIOxPIN3 FIOxPINL FIOxPINU 9.5.5 Fast GPIO port Mask register FIOxMASK (FIO0MASK to FIO4MASK - 0x2009 C010 to 0x2009 C090) This register is used to select port pins that will and will not be affected by write accesses to the FIOxPIN, FIOxSET or FIOxCLR register. Mask register also filters out port’ ...
Page 130
... NXP Semiconductors Aside from the 32-bit long and word only accessible FIOxMASK register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 112, too. Next to providing the same functions as the FIOxMASK register, these additional registers allow easier and faster access to the physical port pins. ...
Page 131
... NXP Semiconductors 9.5.6 GPIO interrupt registers The following registers configure the pins of Port 0 and Port 2 to generate interrupts. 9.5.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0x4002 8080) This read-only register indicates the presence of interrupt pending on all of the GPIO ports that support GPIO interrupts. Only status one bit per port is required. ...
Page 132
... NXP Semiconductors Table 114. GPIO Interrupt Enable for port 0 Rising Edge (IO0IntEnR - 0x4002 8090) bit Bit Symbol 17 P0.17ER 18 P0.18ER 19 P0.19ER 20 P0.20ER 21 P0.21ER 22 P0.22ER 23 P0.23ER 24 P0.24ER 25 P0.25ER 26 P0.26ER 27 P0.27ER 28 P0.28ER 29 P0.29ER 30 P0.30ER 31 - [1] Not available on 80-pin package. 9.5.6.3 GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) Each bit in these read-write registers enables the rising edge interrupt for the corresponding port 2 pin ...
Page 133
... NXP Semiconductors Table 115. GPIO Interrupt Enable for port 2 Rising Edge (IO2IntEnR - 0x4002 80B0) bit Bit Symbol 12 P2.12ER 13 P2.13ER 31:14 - [1] Not available on 80-pin package. 9.5.6.4 GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - 0x4002 8094) Each bit in these read-write registers enables the falling edge interrupt for the corresponding GPIO port 0 pin ...
Page 134
... NXP Semiconductors Table 116. GPIO Interrupt Enable for port 0 Falling Edge (IO0IntEnF - address 0x4002 8094) Bit Symbol 28 P0.28EF 29 P0.29EF 30 P0.30EF 31 - [1] Not available on 80-pin package. 9.5.6.5 GPIO Interrupt Enable for port 2 Falling Edge (IO2IntEnF - 0x4002 80B4) Each bit in these read-write registers enables the falling edge interrupt for the corresponding GPIO port 2 pin ...
Page 135
... NXP Semiconductors 9.5.6.6 GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR - 0x4002 8084) Each bit in these read-only registers indicates the rising edge interrupt status for port 0. Table 118. GPIO Interrupt Status for port 0 Rising Edge Interrupt (IO0IntStatR - 0x4002 8084) Bit ...
Page 136
... NXP Semiconductors 9.5.6.7 GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR - 0x4002 80A4) Each bit in these read-only registers indicates the rising edge interrupt status for port 2. Table 119. GPIO Interrupt Status for port 2 Rising Edge Interrupt (IO2IntStatR - 0x4002 80A4) Bit ...
Page 137
... NXP Semiconductors Table 120. GPIO Interrupt Status for port 0 Falling Edge Interrupt (IO0IntStatF - 0x4002 8088) Bit Symbol 8 P0.8FEI 9 P0.9FEI 10 P0.10FEI 11 P0.11FEI 14: P0.15FEI 16 P0.16FEI 17 P0.17FEI 18 P0.18FEI 19 P0.19FEI 20 P0.20FEI 21 P0.21FEI 22 P0.22FEI 23 P0.23FEI 24 P0.24FEI 25 P0.25FEI 26 P0.26FEI 27 P0.27FEI 28 P0.28FEI 29 P0.29FEI 30 P0.30FEI 31 - [1] Not available on 80-pin package. ...
Page 138
... NXP Semiconductors Table 121. GPIO Interrupt Status for port 2 Falling Edge Interrupt (IO2IntStatF - 0x4002 80A8) Bit Symbol 7 P2.7FEI 8 P2.8FEI 9 P2.9FEI 10 P2.10FEI 11 P2.11FEI 12 P2.12FEI 13 P2.13FEI 31:14 - [1] Not available on 80-pin package. 9.5.6.10 GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C) Writing a 1 into a bit in this write-only register clears any interrupts for the corresponding port 0 pin ...
Page 139
... NXP Semiconductors Table 122. GPIO Interrupt Clear register for port 0 (IO0IntClr - 0x4002 808C)) bit description Bit Symbol 23 P0.23CI 24 P0.24CI 25 P0.25CI 26 P0.26CI 27 P0.27CI 28 P0.28CI 29 P0.29CI 30 P0.30CI 31 - [1] Not available on 80-pin package. 9.5.6.11 GPIO Interrupt Clear register for port 0 (IO2IntClr - 0x4002 80AC) Writing a 1 into a bit in this write-only register clears any interrupts for the corresponding port 2 pin ...
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... NXP Semiconductors 9.6 GPIO usage notes 9.6.1 Example: An instantaneous output of 0s and GPIO port Solution 1: using 32-bit (word) accessible fast GPIO registers FIO0MASK = 0xFFFF00FF ; FIO0PIN = 0x0000A500; Solution 2: using 16-bit (half-word) accessible fast GPIO registers FIO0MASKL = 0x00FF; FIO0PINL = 0xA500; Solution 3: using 8-bit (byte) accessible fast GPIO registers FIO0PIN1 = 0xA5 ...
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UM10360 Chapter 10: LPC17xx Ethernet Rev. 2 — 19 August 2010 10.1 Basic configuration The Ethernet controller is configured using the following registers: 1. Power: In the PCONP register Remark: On reset, the Ethernet block is disabled (PCENET = 0). ...
Page 142
... NXP Semiconductors Table 124. Ethernet acronyms, abbreviations, and definitions Acronym or Abbreviation Frame Half-word LAN MAC MII MIIM Octet Packet PHY RMII Rx TCP/IP Tx VLAN WoL Word 10.3 Features • Ethernet standards support: – Supports 10 or 100 Mbps PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – ...
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... NXP Semiconductors – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision backoff and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • ...
Page 144
... NXP Semiconductors – The transmit DMA manager which reads descriptors and data from memory and writes status to memory. – The transmit retry module handling Ethernet retry and abort situations. – The transmit flow control module which can insert Ethernet pause frames. ...
Page 145
... NXP Semiconductors Hardware in the DMA engine controls how data incoming from the Ethernet MAC is saved to memory, causes fragment related status to be saved, and advances the hardware receive pointer for incoming data. Driver software must handle the disposition of received data, changing of descriptor data addresses (to avoid unnecessary data movement), and advancing the software receive pointer ...
Page 146
... NXP Semiconductors The Ethernet frame consists of the destination address, the source address, an optional VLAN field, the length/type field, the payload and the frame check sequence. Each address consists of 6 bytes where each byte consists of 8 bits. Bits are transferred starting with the least significant bit. ...
Page 147
... NXP Semiconductors Support for IEEE 802.3/clause 31 flow control is implemented in the flow control block. Receive flow control frames are automatically handled by the MAC. Transmit flow control frames can be initiated by software. In half duplex mode, the flow control module will generate back pressure by sending out continuous preamble only, interrupted by pauses to prevent the jabber limit from being exceeded ...
Page 148
... NXP Semiconductors 10.10 Registers and software interface The software interface of the Ethernet block consists of a register view and the format definitions for the transmit and receive descriptors. These two aspects are addressed in the next two subsections. 10.10.1 Register map Table 128 lists the registers, register addresses and other basic information ...
Page 149
... NXP Semiconductors Table 128. Ethernet register definitions Name Description Status Status register. RxDescriptor Receive descriptor base address register. RxStatus Receive status base address register. RxDescriptorNumber Receive number of descriptors register. RxProduceIndex Receive produce index register. RxConsumeIndex Receive consume index register. TxDescriptor Transmit descriptor base address register. ...
Page 150
... NXP Semiconductors 10.11 Ethernet MAC register definitions This section defines the bits in the individual registers of the Ethernet block register map. 10.11.1 MAC Configuration Register 1 (MAC1 - 0x5000 0000) The MAC configuration register 1 (MAC1) has an address of 0x5000 0000. Its bit definition is shown in Table 129. MAC Configuration register 1 (MAC1 - address 0x5000 0000) bit description ...
Page 151
... NXP Semiconductors Table 130. MAC Configuration register 2 (MAC2 - address 0x5000 0004) bit description Bit Symbol Function 0 FULL-DUPLEX When enabled (set to ’1’), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode. 1 FRAME LENGTH When enabled (set to ’1’), both transmit and receive frame lengths are compared to CHECKING the Length/Type field ...
Page 152
... NXP Semiconductors Table 131. Pad operation Type Auto detect VLAN pad pad enable enable MAC2 [7] MAC2 [6] Any x x Any 0 0 Any x 1 Any 1 0 10.11.3 Back-to-Back Inter-Packet-Gap Register (IPGT - 0x5000 0008) The Back-to-Back Inter-Packet-Gap register (IPGT) has an address of 0x5000 0008. Its bit definition is shown in Table 132 ...
Page 153
... NXP Semiconductors 10.11.5 Collision Window / Retry Register (CLRT - 0x5000 0010) The Collision window / Retry register (CLRT) has an address of 0x5000 0010. Its bit definition is shown in Table 134. Collision Window / Retry register (CLRT - address 0x5000 0010) bit description Bit Symbol Function 3:0 RETRANSMISSION ...
Page 154
... NXP Semiconductors Table 137. Test register (TEST - address 0x5000 ) bit description Bit Symbol Function 0 SHORTCUT PAUSE This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time. QUANTA 1 TEST PAUSE This bit causes the MAC Control sublayer to inhibit transmissions, just PAUSE Receive Control frame with a nonzero pause time parameter was received. ...
Page 155
... NXP Semiconductors Table 139. Clock select encoding Clock Select Host Clock divided by 48 Host Clock divided by 52 Host Clock divided by 56 Host Clock divided by 60 Host Clock divided by 64 [1] The maximum AHB clock rate allowed is limited to the maximum CPU clock rate for the device. ...
Page 156
... NXP Semiconductors Table 142. MII Mgmt Write Data register (MWTD - address 0x5000 002C) bit description Bit Symbol 15:0 WRITE DATA 31:16 - 10.11.13 MII Mgmt Read Data Register (MRDD - 0x5000 0030) The MII Mgmt Read Data register (MRDD read-only register with an address of 0x5000 0030 ...
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... NXP Semiconductors 3. Wait for busy bit to be cleared in MIND 4. Write 0 to MCMD 5. Read data from MRDD 10.11.15 Station Address 0 Register (SA0 - 0x5000 0040) The Station Address 0 register (SA0) has an address of 0x5000 0040. The bit definition of this register is shown in Table 145. Station Address register (SA0 - address 0x5000 0040) bit description ...
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... NXP Semiconductors The station address is used for perfect address filtering and for sending pause control frames. For the ordering of the octets in the packet please refer to 10.12 Control register definitions 10.12.1 Command Register (Command - 0x5000 0100) The Command register (Command) register has an address of 0x5000 0100. Its bit definition is shown in Table 148 ...
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... NXP Semiconductors • enabled and the Rx/TxEnable bit is set in the Command register or it just got disabled while still transmitting or receiving a frame. • Also, for the transmit channel, the transmit queue is not empty i.e. ProduceIndex != ConsumeIndex. • Also, for the receive channel, the receive queue is not full i ...
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... NXP Semiconductors Table 152. Receive Number of Descriptors register (RxDescriptor - address 0x5000 0110) bit Bit Symbol 15:0 RxDescriptorNumber 31:16 - The receive number of descriptors register defines the number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors should match the number of statuses. The register uses minus one encoding i.e. if the array has 8 elements, the value in the register should be 7 ...
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... NXP Semiconductors of RxDescriptorNumber has been reached. If the RxProduceIndex equals RxConsumeIndex - 1, the array is full and any further frames being received will cause a buffer overrun error. 10.12.8 Transmit Descriptor Base Address Register (TxDescriptor - 0x5000 011C) The Transmit Descriptor base address register (TxDescriptor) has an address of 0x5000 011C ...
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... NXP Semiconductors The transmit number of descriptors register defines the number of descriptors in the descriptor array for which TxDescriptor is the base address. The number of descriptors should match the number of statuses. The register uses minus one encoding i.e. if the array has 8 elements, the value in the register should be 7. ...
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... NXP Semiconductors distributed over two registers TSV0 and TSV1. These registers are provided for debug purposes, because the communication between driver software and the Ethernet block takes place primarily through the frame descriptors. The status register contents are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are halted ...
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... NXP Semiconductors purposes, because the communication between driver software and the Ethernet block takes place primarily through the frame descriptors. The status register contents are valid as long as the internal status of the MAC is valid and should typically only be read when the transmit and receive processes are TSV1 register ...
Page 165
... NXP Semiconductors Table 162. Receive Status Vector register (RSV - address 0x5000 0160) bit description Bit Symbol 26 Dribble Nibble 27 Control frame 28 PAUSE 29 Unsupported Opcode The current frame was recognized as a Control Frame but 30 VLAN 31 - [1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the " ...
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... NXP Semiconductors 10.13 Receive filter register definitions 10.13.1 Receive Filter Control Register (RxFilterCtrl - 0x5000 0200) The Receive Filter Control register (RxFilterCtrl) has an address of 0x5000 0200. Table 165 lists the definition of the individual bits in the register. Table 165. Receive Filter Control register (RxFilterCtrl - address 0x5000 0200) bit description ...
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... NXP Semiconductors Table 166. Receive Filter WoL Status register (RxFilterWoLStatus - address 0x5000 0204) bit Bit Symbol RxFilterWoL 8 MagicPacketWoL 31:9 - The bits in this register record the cause for a WoL. Bits in RxFilterWoLStatus can be cleared by writing the RxFilterWoLClear register. 10.13.3 Receive Filter WoL Clear Register (RxFilterWoLClear - 0x5000 0208) The Receive Filter Wake-up on LAN Clear register (RxFilterWoLClear write-only register with an address of 0x5000 0208 ...
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... NXP Semiconductors 10.13.5 Hash Filter Table MSBs Register (HashFilterH - 0x5000 0214) The Hash Filter table MSBs register (HashFilterH) has an address of 0x5000 0214. Table 169 lists the bit definitions of the register. Details of Hash filter table use can be found in Section 10.17.10 “Receive filtering” on page Table 169 ...
Page 169
... NXP Semiconductors The interrupt status register is read-only. Setting can be done via the IntSet register. Reset can be accomplished via the IntClear register. 10.14.2 Interrupt Enable Register (IntEnable - 0x5000 0FE4) The Interrupt Enable register (IntEnable) has an address of 0x5000 0FE4. The interrupt enable register bit definition is shown in Table 171 ...
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... NXP Semiconductors Table 172. Interrupt Clear register (IntClear - address 0x5000 0FE8) bit description Bit Symbol 0 RxOverrunIntClr 1 RxErrorIntClr 2 RxFinishedIntClr 3 RxDoneIntClr 4 TxUnderrunIntClr 5 TxErrorIntClr 6 TxFinishedIntClr 7 TxDoneIntClr 11 SoftIntClr 13 WakeupIntClr 31:14 - The interrupt clear register is write-only. Writing bit of the IntClear register clears the corresponding bit in the status register. Writing a 0 will not affect the interrupt status. ...
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... NXP Semiconductors 10.14.5 Power-Down Register (PowerDown - 0x5000 0FF4) The Power-Down register (PowerDown) is used to block all AHB accesses except accesses to the Power-Down register. The register has an address of 0x5000 0FF4. The bit definition of the register is listed in Table 174. Power-Down register (PowerDown - address 0x5000 0FF4) bit description ...
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... NXP Semiconductors 10.15 Descriptor and status formats This section defines the descriptor format for the transmit and receive scatter/gather DMA engines. Each Ethernet frame can consist of one or more fragments. Each fragment corresponds to a single descriptor. The DMA managers in the Ethernet block scatter (for receive) and gather (for transmit) multiple fragments for a single Ethernet frame ...
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... NXP Semiconductors received. The RxConsumeIndex is programmed by software and is the index of the next descriptor that the software receive driver is going to process. When RxProduceIndex == RxConsumeIndex, the receive buffer is empty. When RxProduceIndex == RxConsumeIndex -1 (taking wraparound into account), the receive buffer is full and newly received data would generate an overflow unless the software driver frees up one or more descriptors ...
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... NXP Semiconductors Table 178. Receive Status HashCRC Word Bit Symbol 8:0 SAHashCRC Hash CRC calculated from the source address. 15:9 - 24:16 DAHashCRC Hash CRC calculated from the destination address. 31:25 - The StatusInfo word contains flags returned by the MAC and flags generated by the receive data path reflecting the status of the reception ...
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... NXP Semiconductors [1] The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame ...
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... NXP Semiconductors Two registers, TxConsumeIndex and TxProduceIndex, define the descriptor locations that will be used next by hardware and software. Both register act as counters starting at 0 and wrapping when they reach the value of TxDescriptorNumber. The TxProduceIndex contains the index of the next descriptor that is going to be filled by the software driver. ...
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... NXP Semiconductors The transmit status consists of one word which is the StatusInfo word. It contains flags returned by the MAC and flags generated by the transmit data path reflecting the status of the transmission. Table 183. Transmit status information word Bit Symbol 20:0 - 24:21 CollisionCount 25 Defer ...
Page 178
... NXP Semiconductors To transmit a packet the software driver has to set up the appropriate Control registers and a descriptor to point to the packet data buffer before transferring the packet to hardware by incrementing the TxProduceIndex register. After transmission, hardware will increment TxConsumeIndex and optionally generate an interrupt. The hardware will receive packets from the PHY and apply filtering as configured by the software driver ...
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... NXP Semiconductors The Ethernet block includes two DMA managers. The DMA managers make it possible to transfer frames directly to and from memory with little support from the processor and without the need to trigger an interrupt for each frame. The DMA managers work with arrays of frame descriptors and statuses that are stored in memory ...
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... NXP Semiconductors the one at the next higher, adjacent memory address. Wrap around means that when the Ethernet block has finished reading/writing the last descriptor/status of the array (with the highest memory address), the next descriptor/status it reads/writes is the first descriptor/status of the array at the base address of the array. ...
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... NXP Semiconductors to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit frames are gathered from multiple fragments in memory and receive frames can be scattered to multiple fragments in memory. By stringing together fragments it is possible to create large frames from small memory areas. Another use of fragments able to locate a frame header and frame payload in different places and to concatenate them without copy operations in the device driver ...
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... NXP Semiconductors Please note that the transmit descriptors, receive descriptors and receive statuses are 8 bytes each while the transmit statuses are 4 bytes each. All descriptor arrays and transmit statuses need to be aligned on 4 byte boundaries; receive status arrays need to be aligned on 8 byte boundaries. The number of descriptors in the descriptor arrays needs to be written to the TxDescriptorNumber/RxDescriptorNumber registers using a -1 encoding i ...
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... NXP Semiconductors After writing the descriptor the descriptor needs to be handed over to the hardware by incrementing (and possibly wrapping) the TxProduceIndex register. If the transmit data path is disabled, the device driver should not forget to enable the transmit data path by setting the TxEnable bit in the Command register. ...
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... NXP Semiconductors frame descriptors, and sends them out as one Ethernet frame on the Ethernet connection. When the Tx DMA manager finds a descriptor with the Last bit in the Control field set to 1, this indicates the last fragment of the frame and thus the end of the frame is found. ...
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... NXP Semiconductors The transmission can generate several types of errors: LateCollision, ExcessiveCollision, ExcessiveDefer, Underrun, and NoDescriptor. All have corresponding bits in the transmission StatusInfo word. In addition to the separate bits in the StatusInfo word, LateCollision, ExcessiveCollision, and ExcessiveDefer are ORed together into the Error bit of the Status. Errors are also propagated to the IntStatus register; the TxError bit in the IntStatus register is set in the case of a LateCollision, ExcessiveCollision, ExcessiveDefer, or NoDescriptor error ...
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... NXP Semiconductors • In the case of a transmission error (LateCollision, ExcessiveCollision, or ExcessiveDefer multi-fragment frame where the device driver did provide the initial fragments but did not provide the rest of the fragments (NoDescriptor the case of a nonfatal overrun, the hardware will set the TxErrorInt bit of the IntStatus register ...
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... NXP Semiconductors boundary. Since the number of descriptors matches the number of statuses the status array consists of four elements; the array is 4x1x4 bytes and aligned byte address boundary. The device driver writes the base address of the descriptor array (0x2008 10EC) to the TxDescriptor register and the base address of the status array (0x2008 11F8) to the TxStatus register ...
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... NXP Semiconductors After transmitting each fragment of the frame the Tx DMA will write the status of the fragment’s transmission. Statuses for all but the last fragment in the frame will be written as soon as the data in the frame has been accepted by the Tx DMA manager. The status for the last fragment in the frame will only be written after the transmission has completed on the Ethernet connection ...
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... NXP Semiconductors Rx DMA manager reads Rx descriptor arrays When the RxEnable bit in the Command register is set, the Rx DMA manager reads the descriptors from memory at the address determined by RxDescriptor and RxProduceIndex. The Ethernet block will start reading descriptors even before actual receive data arrives on the RMII interface (descriptor prefetching). The block size of the descriptors to be read is determined by the total number of descriptors owned by the hardware: RxConsumeIndex - RxProduceIndex - 1 ...
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... NXP Semiconductors If the descriptor is for the last fragment of a frame (or for the whole frame if there are no fragments), then depending on the success or failure of the frame reception, error flags (Error, NoDescriptor, Overrun, AlignmentError, RangeError, LengthError, SymbolError, or CRCError) are set in StatusInfo. The RxSize field is set to the number of bytes actually written to the fragment buffer, -1 encoded ...
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... NXP Semiconductors receive errors cannot be reported in the receiver Status arrays which corrupts the hardware state; the errors will still be reported in the IntStatus register’s Overrun bit. The RxReset bit in the Command register should be used to soft reset the hardware. Device drivers should catch the above receive errors and take action. ...
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... NXP Semiconductors RxDescriptor 0x200810EC 0x200810EC PACKET 0x20081409 0x200810F0 1 CONTROL 7 0x200810F4 PACKET 0x20081411 0x200810F8 1 CONTROL 7 PACKET 0x200810FC 0x20081419 CONTROL 1 7 0x20081100 PACKET 0x20081104 0x20081325 CONTROL 1 7 0x20081108 descriptor array Fig 22. Receive Example Memory and Registers After reset, the values of the DMA registers will be zero. During initialization, the device driver will allocate the descriptor and status array in memory. In this example, an array of four descriptors is allocated ...
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... NXP Semiconductors continuous memory space; even when a frame is distributed over multiple fragments it will typically linear, continuous memory space; when the descriptors wrap at the end of the descriptor array the frame will not continuous memory space. The device driver should enable the receive process by writing the RxEnable bit of the Command register, after which the MAC needs to be enabled by writing the ‘ ...
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... NXP Semiconductors Each four pairs of bits transferred on the RMII interface are transferred as a byte on the data write interface after being delayed by 128 or 136 cycles for filtering by the receive filter and buffer modules. The Ethernet block removes preamble, frame start delimiter, and CRC from the data and checks the CRC ...
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... NXP Semiconductors 10.17.7 Duplex modes The Ethernet block can operate in full duplex and half duplex mode. Half or full duplex mode needs to be configured by the device driver software during initialization. For a full duplex connection the FullDuplex bit of the Command register needs to be set to 1 and the FULL-DUPLEX bit of the MAC2 configuration register needs to be set to 1 ...
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... NXP Semiconductors If the MAC is operating in full-duplex mode, then setting the TxFlowControl bit of the Command register will start a pause frame transmission. The value inserted into the pause-timer value field of transmitted pause frames is programmed via the PauseTimer[15:0] bits in the FlowControlCounter register. When the TxFlowControl bit is de-asserted, another pause frame having a pause-timer value of 0x0000 is automatically sent to abort flow control and resume transmission ...
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... NXP Semiconductors device driver PauseTimer register MirrorCounter TxFlowCtl writes pause control RMII normal frame transmit transmission transmission MirrorCounter (1/515 bit slots) RMII normal receive receive 0 50 100 Fig 23. Transmit Flow Control In this example, a frame is received while transmitting another frame (full duplex.) The ...
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... NXP Semiconductors 10.17.10 Receive filtering Features of receive filtering The Ethernet MAC has several receive packet filtering functions that can be configured from the software driver: • Perfect address filter: allows packets with a perfectly matching station address to be identified and passed to the software driver. ...
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... NXP Semiconductors AcceptUnicastEn AcceptMulticastEn IMPERFECT AcceptMulticastHashEn HASH FILTER AcceptUnicastHashEn HashFilter Fig 24. Receive filter block diagram Unicast, broadcast and multicast Generic filtering based on the type of frame (unicast, multicast or broadcast) can be programmed using the AcceptUnicastEn, AcceptMulticastEn, or AcceptBroadcastEn bits of the RxFilterCtrl register. Setting the AcceptUnicast, AcceptMulticast, and AcceptBroadcast bits causes all frames of types unicast, multicast and broadcast, respectively accepted, ignoring the Ethernet destination address in the frame ...
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... NXP Semiconductors • Hash function: – The standard Ethernet cyclic redundancy check (CRC) function is calculated from the 6 byte destination address in the Ethernet frame (this CRC is calculated anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of the 32-bit CRC result are taken to form the hash. The 6-bit hash is used to access the hash table used as an index in the 64-bit HashFilter register that has been programmed with accept values ...