LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 87
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 62.
Table 63.
Table 64.
UM10360
User manual
Bit
2:0
7:3
10:8
15:11 IP_TIMER0
18:16 Unimplemented
23:19 IP_TIMER1
26:24 Unimplemented
31:27 IP_TIMER2
Bit
2:0
7:3
10:8
15:11 IP_UART0
18:16 Unimplemented
23:19 IP_UART1
26:24 Unimplemented
31:27 IP_UART2
Bit
2:0
7:3
10:8
15:11 IP_PWM
18:16 Unimplemented
23:19 IP_I2C0
26:24 Unimplemented
31:27 IP_I2C1
Name
Unimplemented
IP_WDT
Unimplemented
Name
Unimplemented
IP_TIMER3
Unimplemented
Name
Unimplemented
IP_UART3
Unimplemented
Interrupt Priority Register 0 (IPR0 - 0xE000 E400)
Interrupt Priority Register 1 (IPR1 - 0xE000 E404)
Interrupt Priority Register 2 (IPR2 - 0xE000 E408)
6.5.12 Interrupt Priority Register 1 (IPR1 - 0xE000 E404)
6.5.13 Interrupt Priority Register 2 (IPR2 - 0xE000 E408)
6.5.11 Interrupt Priority Register 0 (IPR0 - 0xE000 E400)
The IPR0 register controls the priority of the first 4 peripheral interrupts. Each interrupt can
have one of 32 priorities, where 0 is the highest priority.
The IPR1 register controls the priority of the second group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
The IPR2 register controls the priority of the third group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Function
These bits ignore writes, and read as 0.
Watchdog Timer Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
Timer 0 Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
Timer 1 Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
Timer 2 Interrupt Priority. See functional description for bits 7-3.
Function
These bits ignore writes, and read as 0.
Timer 3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
UART0 Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
UART1 Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
UART2 Interrupt Priority. See functional description for bits 7-3.
Function
These bits ignore writes, and read as 0.
UART3 Interrupt Priority. 0 = highest priority. 31 (0x1F) = lowest priority.
These bits ignore writes, and read as 0.
PWM Interrupt Priority. See functional description for bits 7-3.
These bits ignore writes, and read as 0.
I
These bits ignore writes, and read as 0.
I
2
2
C0 Interrupt Priority. See functional description for bits 7-3.
C1 Interrupt Priority. See functional description for bits 7-3.
All information provided in this document is subject to legal disclaimers.
Chapter 6: LPC17xx Nested Vectored Interrupt Controller (NVIC)
Rev. 2 — 19 August 2010
UM10360
© NXP B.V. 2010. All rights reserved.
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