LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 361

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 321. CAN Interrupt Enable Register (CAN1IER - address 0x4004 4010, CAN2IER - address 0x4004 8010) bit
Table 322. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit
UM10360
User manual
Bit
3
4
5
6
7
8
9
10
31:11 -
Bit
9:0
13:10 -
15:14 SJW
19:16 TESG1
22:20 TESG2
Symbol Value Function
BRP
Symbol Function
DOIE
WUIE
EPIE
ALIE
BEIE
IDIE
TIE2
TIE3
description
description
16.7.6 CAN Bus Timing Register (CAN1BTR - 0x4004 4014, CAN2BTR -
Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the
CAN Controller requests the respective interrupt.
Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt
is requested.
Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error
active to error passive or vice versa, the respective interrupt is requested.
Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective
interrupt is requested.
Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the
respective interrupt.
ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller
requests the respective interrupt.
Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted
out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission
command), the CAN Controller requests the respective interrupt.
Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted
out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission
command), the CAN Controller requests the respective interrupt.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
0x4004 8014)
This register controls how various CAN timings are derived from the APB clock. It defines
the values of the Baud Rate Prescaler (BRP) and the Synchronization Jump Width (SJW).
Furthermore, it defines the length of the bit period, the location of the sample point and the
number of samples to be taken at each sample point. It can be read at any time but can
only be written if the RM bit in CANmod is 1.
Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the
CAN clock.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The Synchronization Jump Width is (this value plus one) CAN clocks.
The delay from the nominal Sync point to the sample point is (this value plus one)
CAN clocks.
The delay from the sample point to the next nominal sync point is (this value plus one)
CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3)
CAN clocks.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 16: LPC17xx CAN1/2
UM10360
© NXP B.V. 2010. All rights reserved.
Reset
Value
0
0
0
0
0
0
0
0
NA
Reset
Value
0
NA
0
1100
001
361 of 840
RM
Set
X
X
X
X
RM
Set
X
X
X
X
X
X
X
X