LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 253

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
11.14 Slave mode operation
UM10360
User manual
11.14.1 Interrupt generation
10. Set default USB address to 0x0 and DEV_EN to 1 using the SIE Set Address
11. Set CON bit to 1 to make CONNECT active using the SIE Set Device Status
The configuration of the endpoints varies depending on the software application. By
default, all the endpoints are disabled except control endpoints EP0 and EP1. Additional
endpoints are enabled and configured by software after a SET_CONFIGURATION or
SET_INTERFACE device request is received from the host.
In Slave mode, the CPU transfers data between RAM and the endpoint buffer using the
Register Interface.
In slave mode, data packet transfer between RAM and an endpoint buffer can be initiated
in response to an endpoint interrupt. Endpoint interrupts are enabled using the
USBEpIntEn register, and are observable in the USBEpIntSt register.
6. Set USBEpIn and USBMaxPSize registers for EP0 and EP1, and wait until the
7. Enable endpoint interrupts (Slave mode):
8. Configure the DMA (DMA mode):
9. Install USB interrupt handler in the NVIC by writing its address to the appropriate
EP_RLZED bit in USBDevIntSt is set so that EP0 and EP1 are realized.
– Clear all endpoint interrupts using USBEpIntClr.
– Clear any device interrupts using USBDevIntClr.
– Enable Slave mode for the desired endpoints by setting the corresponding bits in
– Set the priority of each enabled interrupt using USBEpIntPri.
– Configure the desired interrupt mode using the SIE Set Mode command.
– Enable device interrupts using USBDevIntEn (normally DEV_STAT, EP_SLOW,
– Disable DMA operation for all endpoints using USBEpDMADis.
– Clear any pending DMA requests using USBDMARClr.
– Clear all DMA interrupts using USBEoTIntClr, USBNDDRIntClr, and
– Prepare the UDCA in system memory.
– Write the desired address for the UDCA to USBUDCAH.
– Enable the desired endpoints for DMA operation using USBEpDMAEn.
– Set EOT, DDR, and ERR bits in USBDMAIntEn.
vector table location and enabling the USB interrupt in the NVIC.
command. A bus reset will also cause this to happen.
command.
USBEpIntEn.
and possibly EP_FAST).
USBSysErrIntClr.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 11: LPC17xx USB device controller
UM10360
© NXP B.V. 2010. All rights reserved.
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