LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 101

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 73.
UM10360
User manual
Symbol
P2[4] / PWM1[5] /
DSR1 /
TRACEDATA[1]
P2[5] / PWM1[6] /
DTR1 /
TRACEDATA[0]
P2[6] / PCAP1[0] /
RI1 / TRACECLK
P2[7] / RD2 /
RTS1
P2[8] / TD2 /
TXD2 / ENET_MDC
P2[9] /
USB_CONNECT /
RXD2 /
ENET_MDIO
P2[10] / EINT0 /
NMI
P2[11] / EINT1 /
I2STX_CLK
Pin description
LQFP
100
69
68
67
66
65
64
53
52
…continued
LQFP
80
54
53
52
51
50
49
41
-
Type Description
I/O
O
I
O
I/O
O
O
O
I/O
I
I
O
I/O
I
O
I/O
O
O
O
I/O
O
I
I/O
I/O
I
I
I/O
I
I/O
All information provided in this document is subject to legal disclaimers.
P2[4] — General purpose digital input/output pin.
PWM1[5] — Pulse Width Modulator 1, channel 5 output.
DSR1 — Data Set Ready input for UART1.
TRACEDATA[1] — Trace data, bit 1.
P2[5] — General purpose digital input/output pin.
PWM1[6] — Pulse Width Modulator 1, channel 6 output.
DTR1 — Data Terminal Ready output for UART1. Can also be configured
to be an RS-485/EIA-485 output enable signal.
TRACEDATA[0] — Trace data, bit 0.
P2[6] — General purpose digital input/output pin.
PCAP1[0] — Capture input for PWM1, channel 0.
RI1 — Ring Indicator input for UART1.
TRACECLK — Trace Clock.
P2[7] — General purpose digital input/output pin.
RD2 — CAN2 receiver input.
RTS1 — Request to Send output for UART1. Can also be configured to be
an RS-485/EIA-485 output enable signal.
P2[8] — General purpose digital input/output pin.
TD2 — CAN2 transmitter output.
TXD2 — Transmitter output for UART2.
ENET_MDC — Ethernet MIIM clock.
P2[9] — General purpose digital input/output pin.
USB_CONNECT — Signal used to switch an external 1.5 k Ω resistor
under software control. Used with the SoftConnect USB feature.
RXD2 — Receiver input for UART2.
ENET_MDIO — Ethernet MIIM data input and output.
P2[10] — General purpose digital input/output pin. 5 V tolerant pad with 5
ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
Note: A LOW on this pin while RESET is LOW forces the on-chip
bootloader to take over control of the part after a reset and go into ISP
mode. See
EINT0 — External interrupt 0 input.
NMI — Non-maskable interrupt input.
P2[11] — General purpose digital input/output pin. 5 V tolerant pad with 5
ns glitch filter providing digital I/O functions with TTL levels and hysteresis.
EINT1 — External interrupt 1 input.
I2STX_CLK — Transmit Clock. It is driven by the master and received by
the slave. Corresponds to the signal SCK in the I
Rev. 2 — 19 August 2010
Section
32.1.
Chapter 7: LPC17xx Pin configuration
2
S bus specification .
UM10360
© NXP B.V. 2010. All rights reserved.
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