LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 568

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
27.7 RTC usage notes
UM10360
User manual
27.6.6.1 General purpose registers 0 to 4 (GPREG0 to GPREG4 - addresses
27.6.6 General purpose registers
27.6.7 Alarm register group
0x4002 4044 to 0x4002 4054)
These registers can be used to store important information when the main power supply is
off. The value in these registers is not affected by chip reset.
Table 520. General purpose registers 0 to 4 (GPREG0 to GPREG4 - addresses 0x4002 4044
The alarm registers are shown in
with the time counters. If all the unmasked (See
(AMR - 0x4002 4010)” on page
counters then an interrupt is generated. The interrupt is cleared when a 1 is written to bit 1
of the Interrupt Location Register (ILR[1]).
Table 521. Alarm registers
If the RTC is used, V
external battery), or left floating. The RTC domain will always be internally powered if
V
available on either V
register contents. If both V
be lost. RTC incrementation will stop or be unpredictable if the clock source is lost,
interrupted, or altered.
Bit
31:0
Name
ALSEC
ALMIN
ALHOUR
ALDOM
ALDOW
ALDOY
ALMON
ALYEAR
DD(REG)(3V3)
Symbol
GP0 to GP4
to 0x4002 4054) bit description
Size
6
6
5
5
3
9
4
12
is present, even if there is no power applied to V
All information provided in this document is subject to legal disclaimers.
Chapter 27: LPC17xx Real-Time Clock (RTC) and backup registers
Alarm value for Months
Description
Alarm value for Seconds
Alarm value for Minutes
Alarm value for Hours
Alarm value for Day of Month
Alarm value for Day of Week
Alarm value for Day of Year
Alarm value for Years
DD(REG)(3V3)
BAT
Rev. 2 — 19 August 2010
Description
General purpose storage.
may be connected to an independent power supply (typically an
DD(REG)(3V3)
563) alarm registers match their corresponding time
or V
Table
BAT
and V
521. The values in these registers are compared
, the RTC will retain its time value and the backup
BAT
are not present, all RTC information will
Section 27.6.2.4 “Alarm Mask Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BAT
. As long as power is
UM10360
© NXP B.V. 2010. All rights reserved.
Address
0x4002 4060
0x4002 4064
0x4002 4068
0x4002 406C
0x4002 4070
0x4002 4074
0x4002 4078
0x4002 407C
568 of 840
Reset
value
N/A