LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 811

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 446: PWM Interrupt Register (PWM1IR - address
Table 447. PWM Timer Control Register (PWM1TCR
Table 448. PWM Count control Register (PWM1CTCR -
Table 449: Match Control Register (PWM1MCR - address
Table 450: PWM Capture Control Register (PWM1CCR -
Table 451: PWM Control Register (PWM1PCR - address
Table 452: PWM Latch Enable Register (PWM1LER -
Table 453. Pin summary . . . . . . . . . . . . . . . . . . . . . . . . .522
Table 454. Motor Control Pulse Width Modulator (MCPWM)
Table 455. MCPWM Control read address (MCCON -
Table 456. MCPWM Control set address (MCCON_SET -
Table 457. MCPWM Control clear address (MCCON_CLR -
Table 458. MCPWM Capture Control read address
Table 459. MCPWM Capture Control set address
Table 460. MCPWM Capture control clear register
Table 461. Motor Control PWM interrupts . . . . . . . . . . . .529
Table 462. Interrupt sources bit allocation table . . . . . . .529
Table 463. MCPWM Interrupt Enable read address
Table 464. PWM interrupt enable set register
Table 465. PWM interrupt enable clear register
Table 466. MCPWM Interrupt Flags read address (MCINTF -
Table 467. MCPWM Interrupt Flags set address
Table 468. MCPWM Interrupt Flags clear address
Table 469. MCPWM Count Control read address
Table 470. MCPWM Count Control set address
Table 471. MCPWM Count Control clear address
Table 472. MCPWM Timer/Counter 0-2 registers (MCTC0-2
UM10360
User manual
0x4001 8000) bit description . . . . . . . . . . . . .515
address 0x4001 8004) bit description. . . . . . .516
address 0x4001 8070) bit description. . . . . . .516
0x4001 8014) bit description . . . . . . . . . . . . .517
address 0x4001 8028) bit description. . . . . . .518
0x4001 804C) bit description . . . . . . . . . . . . .519
address 0x4001 8050) bit description. . . . . . .520
register map . . . . . . . . . . . . . . . . . . . . . . . . . .525
0x400B 8000) bit description . . . . . . . . . . . . .526
0x400B 8004) bit description . . . . . . . . . . . . .527
0x400B 8008) bit description . . . . . . . . . . . . .528
(MCCAPCON - 0x400B 800C) bit description 528
(MCCAPCON_SET - 0x400B 8010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .529
(MCCAPCON_CLR - address 0x400B 8014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .529
(MCINTEN - 0x400B 8050) bit description . . .529
(MCINTEN_SET - address 0x400B 8054) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .530
(MCINTEN_CLR - address 0x400B 8058) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .530
0x400B 8068) bit description . . . . . . . . . . . . .530
(PWMINTF_SET - 0x400B 806C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .530
(PWMINTF_CLR - 0x400B 8070) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .531
(MCCNTCON - 0x400B 805C) bit description 531
(MCCNTCON_SET - 0x400B 8060) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .532
(MCCAPCON_CLR - 0x400B 8064) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .532
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Table 473. MCPWM Limit 0-2 registers (MCLIM0-2 -
Table 474. MCPWM Match 0-2 registers (MCMAT0-2 -
Table 475. MCPWM Dead-time register (MCDT - address
Table 476. MCPWM Commutation Pattern register (MCCP -
Table 477. MCPWM Capture read addresses (MCCAP0/1/2
Table 478. MCPWM Capture clear address (CAP_CLR -
Table 479. Encoder states . . . . . . . . . . . . . . . . . . . . . . . 545
Table 480. Encoder state transitions
Table 481. Encoder direction . . . . . . . . . . . . . . . . . . . . . 546
Table 482. QEI pin description . . . . . . . . . . . . . . . . . . . . 548
Table 483. QEI Register summary . . . . . . . . . . . . . . . . . 549
Table 484: QEI Control register (QEICON - address
Table 485: QEI Configuration register (QEICONF - address
Table 486: QEI Interrupt Status register (QEISTAT - address
Table 487: QEI Position register (QEIPOS - address
Table 488: QEI Maximum Position register (QEIMAXPOS -
Table 489: QEI Position Compare register 0 (CMPOS0 -
Table 490: QEI Position Compare register 1 (CMPOS1 -
Table 491: QEI Position Compare register 2 (CMPOS2 -
Table 492: QEI Index Count register (CMPOS - address
Table 493: QEI Index Compare register (CMPOS - address
Table 494: QEI Timer Load register (QEILOAD - address
Table 495: QEI Timer register (QEITIME - address
Table 496: QEI Velocity register (QEIVEL - address
Table 497: QEI Velocity Capture register (QEICAP - address
Table 498: QEI Velocity Compare register (VELCOMP -
Table 499: QEI Digital Filter register (FILTER - address
Table 500: QEI Interrupt Status register (QEIINTSTAT -
Table 501: QEI Interrupt Set register (QEISET - address
- 0x400B 8018, 0x400B 801C, 0x400B 8020) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
0x400B 8024, 0x400B 8028, 0x400B 802C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
addresses 0x400B 8030, 0x400B 8034,
0x400B 8038) bit description . . . . . . . . . . . . . 534
0x400B 803C) bit description. . . . . . . . . . . . . 535
address 0x400B 8040) bit description . . . . . . 535
- 0x400B 8044, 0x400B 8048, 0x400B 804C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
0x400B 8074) bit description . . . . . . . . . . . . . 536
0x400B C000) bit description. . . . . . . . . . . . . 550
0x400B C008) bit description. . . . . . . . . . . . . 550
0x400B C004) bit description. . . . . . . . . . . . . 550
0x400B C00C) bit description . . . . . . . . . . . . 551
address 0x400B C010) bit description . . . . . . 551
address 0x400B C014) bit description . . . . . . 551
address 0x400B C018) bit description . . . . . . 551
address 0x400B C01C) bit description . . . . . 552
0x400B C020) bit description. . . . . . . . . . . . . 552
0x400B C024) bit description. . . . . . . . . . . . . 552
0x400B C028) bit description. . . . . . . . . . . . . 552
0x400B C02C) bit description . . . . . . . . . . . . 552
0x400B C030) bit description. . . . . . . . . . . . . 553
0x400B C034) bit description. . . . . . . . . . . . . 553
address 0x400B C038) bit description . . . . . . 553
0x400B C03C) bit description . . . . . . . . . . . . 553
address 0x400B CFE0) bit description . . . . . 554
0x400B CFEC) bit description . . . . . . . . . . . . 554
Chapter 35: Supplementary information
[1]
UM10360
. . . . . . . . . . . . . . 545
© NXP B.V. 2010. All rights reserved.
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