LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 643

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
33.6 Debug memory re-mapping
33.7 JTAG TAP Identification
UM10360
User manual
33.6.1 Memory Mapping Control register (MEMMAP - 0x400F C040)
Another issue is that debug mode changes the way in which reduced power modes are
handled by the Cortex-M3 CPU. This causes power modes at the device level to be
different from normal modes operation. These differences mean that power
measurements should not be made while debugging, the results will be higher than during
normal operation in an application.
During a debugging session, the System Tick Timer and the Repetitive Interrupt Timers
are automatically stopped whenever the CPU is stopped. Other peripherals are not
affected. If the Repetitive Interrupt Timer is configured such that its PCLK rate is lower
than the CPU clock rate, the RIT may not increment predictably during some debug
operations, such as single stepping.
Debugging is disabled if code read protection is enabled.
Following chip reset, a portion of the Boot ROM is mapped to address 0 so that it will be
automatically executed. The Boot ROM switches the map to point to Flash memory prior
to user code being executed. In this way a user normally does not need to know that this
re-mapping occurs.
However, when a debugger halts CPU execution immediately following reset, the Boot
ROM is still mapped to address 0 and can cause confusion. Ideally, the debugger should
correct the mapping automatically in this case, so that a user does not need to deal with it.
The MEMMAP register allows switch the mapping of the bottom of memory, including
default reset and interrupt vectors, between the Boot ROM and the bottom of on-chip
Flash memory.
Table 611. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
The JTAG TAP controller contains device ID that can be used by debugging software to
identify the general type of device. More detailed device information is available through
ISP/IAP commands (see
value is 0x4BA0 0477.
Bit
0
31:1
Symbol
MAP
-
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
Chapter 33: LPC17xx JTAG, Serial Wire Debug (SWD), and Trace
Rev. 2 — 19 August 2010
Memory map control.
Boot mode. A portion of the Boot ROM is mapped to address 0.
User mode. The on-chip Flash memory is mapped to address 0.
Reserved. The value read from a reserved bit is not defined.
Section 32.7
and
Section
32.8). For the LPC17xx family, this ID
UM10360
© NXP B.V. 2010. All rights reserved.
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Reset
value
0
NA