LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 743

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
34.3.2.6.1 Little-endian format
34.3.2.6 Memory endianness
34.3.2.7 Synchronization primitives
The processor views memory as a linear collection of bytes numbered in ascending order
from zero. For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the
second stored word.
memory.
In little-endian format, the processor stores the least significant byte of a word at the
lowest-numbered byte, and the most significant byte at the highest-numbered byte. For
example:
The Cortex-M3 instruction set includes pairs of synchronization primitives. These
provide a non-blocking mechanism that a thread or process can use to obtain exclusive
access to a memory location. Software can use them to perform a guaranteed
read-modify-write memory update sequence, or for a semaphore mechanism.
A pair of synchronization primitives comprises:
The pairs of Load-Exclusive and Store-Exclusive instructions are:
Software must use a Load-Exclusive instruction with the corresponding Store-Exclusive
instruction.
•
•
•
•
•
A Load-Exclusive instruction
Used to read the value of a memory location, requesting exclusive access to that
location.
A Store-Exclusive instruction
Used to attempt to write to the same memory location, returning a status bit to a
register. If this bit is:
– 0: it indicates that the thread or process gained exclusive access to the memory,
– 1: it indicates that the thread or process did not gain exclusive access to the
the word instructions LDREX and STREX
the halfword instructions LDREXH and STREXH
the byte instructions LDREXB and STREXB.
and the write succeeds,
memory, and no write is performed,
All information provided in this document is subject to legal disclaimers.
Section 34.3.2.6.1
Rev. 2 — 19 August 2010
Address A
A+1
A+2
A+3
describes how words of data are stored in
7
Chapter 34: Appendix: Cortex-M3 user guide
Memory
B0
B1
B2
B3
0
lsbyte
msbyte
31
B3
24 23
B2
UM10360
Register
© NXP B.V. 2010. All rights reserved.
16 15
B1
8 7
743 of 840
B0
0