LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 239

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 230. USB DMA Interrupt Status register (USBDMAIntSt - address 0x5000 C290) bit description
Table 231. USB DMA Interrupt Enable register (USBDMAIntEn - address 0x5000 C294) bit description
Table 232. USB End of Transfer Interrupt Status register (USBEoTIntSt - address 0x5000 C2A0s) bit description
UM10360
User manual
Bit
2
31:3
Bit
0
1
2
31:3
Bit
31:0
Symbol
ERR
-
Symbol
EPxx
Symbol
EOT
NDDR
ERR
-
11.10.7.10 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0x5000 C2A0)
11.10.7.11 USB End of Transfer Interrupt Clear register (USBEoTIntClr - 0x5000 C2A4)
11.10.7.9 USB DMA Interrupt Enable register (USBDMAIntEn - 0x5000 C294)
Value
0
1
Value Description
0
1
-
Value Description
0
1
0
1
0
1
-
Writing a one to a bit in this register enables the corresponding bit in USBDMAIntSt to
generate an interrupt on the USB_INT_REQ_DMA interrupt line when set. USBDMAIntEn
is a read/write register.
When the DMA transfer completes for the current DMA descriptor, either normally
(descriptor is retired) or because of an error, the bit corresponding to the endpoint is set in
this register. The cause of the interrupt is recorded in the DD_status field of the descriptor.
USBEoTIntSt is a read-only register.
Writing one to a bit in this register clears the corresponding bit in the USBEoTIntSt
register. Writing zero has no effect. USBEoTIntClr is a write-only register.
Description
Endpoint xx (2 ≤ xx ≤ 31) End of Transfer Interrupt request.
There is no End of Transfer interrupt request for endpoint xx.
There is an End of Transfer Interrupt request for endpoint xx.
System Error Interrupt bit.
All bits in the USBSysErrIntSt register are 0.
At least one bit in the USBSysErrIntSt is set.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
End of Transfer Interrupt enable bit.
The End of Transfer Interrupt is disabled.
The End of Transfer Interrupt is enabled.
New DD Request Interrupt enable bit.
The New DD Request Interrupt is disabled.
The New DD Request Interrupt is enabled.
System Error Interrupt enable bit.
The System Error Interrupt is disabled.
The System Error Interrupt is enabled.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 11: LPC17xx USB device controller
UM10360
© NXP B.V. 2010. All rights reserved.
Reset value
0
NA
Reset value
0
0
0
NA
Reset value
0
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