LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 181
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10360
User manual
10.17.2 Initialization
to a fragment of a frame. By using fragments, scatter/gather DMA can be done: transmit
frames are gathered from multiple fragments in memory and receive frames can be
scattered to multiple fragments in memory.
By stringing together fragments it is possible to create large frames from small memory
areas. Another use of fragments is to be able to locate a frame header and frame payload
in different places and to concatenate them without copy operations in the device driver.
For transmissions, the Last bit in the descriptor Control field indicates if the fragment is the
last in a frame; for receive frames, the LastFrag bit in the StatusInfo field of the status
words indicates if the fragment is the last in the frame. If the Last(Frag) bit is 0 the next
descriptor belongs to the same Ethernet frame, If the Last(Frag) bit is 1 the next descriptor
is a new Ethernet frame.
After reset, the Ethernet software driver needs to initialize the Ethernet block. During
initialization the software needs to:
Depending on the PHY, the software needs to initialize registers in the PHY via the MII
Management interface. The software can read and write PHY registers by programming
the MCFG, MCMD, MADR registers of the MAC. Write data should be written to the
MWTD register; read data and status information can be read from the MRDD and MIND
registers.
The Ethernet block supports RMII PHYs. During initialization software must select RMII
mode by programming the Command register.
Before switching to RMII mode the default soft reset (MAC1 register bit 15) has to be
de-asserted. The phy_ref_clk must be running and internally connected during this
operation.
Transmit and receive DMA engines should be initialized by the device driver by allocating
the descriptor and status arrays in memory. Transmit and receive functions have their own
dedicated descriptor and status arrays. The base addresses of these arrays need to be
programmed in the TxDescriptor/TxStatus and RxDescriptor/RxStatus registers. The
number of descriptors in an array matches the number of statuses in an array.
•
•
•
•
•
•
Remove the soft reset condition from the MAC
Configure the PHY via the MIIM interface of the MAC.
Remark: it is important to configure the PHY and insure that reference clocks
(ENET_REF_CLK signal in RMII mode, or both ENET_RX_CLK and ENET_TX_CLK
signals in MII mode) are present at the external pins and connected to the EMAC
module (selecting the appropriate pins using the PINSEL registers) prior to continuing
with Ethernet configuration. Otherwise the CPU can become locked and no further
functionality will be possible. This will cause JTAG lose communication with the target,
if debug mode is being used.
Select RMII mode
Configure the transmit and receive DMA engines, including the descriptor arrays
Configure the host registers (MAC1,MAC2 etc.) in the MAC
Enable the receive and transmit data paths
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
181 of 840
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