LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 426
![IC ARM CORTEX MCU 512K 100-LQFP](/photos/6/65/66516/568-100-lqfp_sot407-1_sml.jpg)
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- OM11043 PDF datasheet
- LPC1767FBD100551 PDF datasheet #2
- LPC1767FBD100551 PDF datasheet #3
- LPC1769FBD100551 PDF datasheet #4
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NXP Semiconductors
UM10360
User manual
18.6.10 SSPn DMA Control Register (SSP0DMACR - 0x4008 8024,
18.6.9 SSPn Interrupt Clear Register (SSP0ICR - 0x4008 8020, SSP1ICR -
Table 377: SSPn Masked Interrupt Status register (SSPnMIS -address 0x4008 801C, SSP1MIS
0x4003 0020)
Software can write one or more one(s) to this write-only register, to clear the
corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt
conditions can be cleared by writing or reading the appropriate FIFO, or disabled by
clearing the corresponding bit in SSPnIMSC.
Table 378: SSPn interrupt Clear Register (SSP0ICR - address 0x4008 8020, SSP1ICR -
SSP1DMACR - 0x4003 0024)
The SSPnDMACR register is the DMA control register. It is a read/write register.
Bit
0
1
2
3
31:4
Bit
0
1
31:2
Symbol
RORIC
RTIC
-
Symbol
RORMIS
RTMIS
RXMIS
TXMIS
-
- 0x4003 001C) bit description
0x4003 0020) bit description
All information provided in this document is subject to legal disclaimers.
Description
Writing a 1 to this bit clears the “frame was received when RxFIFO was
full” interrupt.
Writing a 1 to this bit clears the "Rx FIFO was not empty and has not
been read for a timeout period" interrupt. The timeout period is the same
for master and slave modes and is determined by the SSP bit rate: 32
bits at PCLK / (CPSDVSR × [SCR+1]).
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Description
This bit is 1 if another frame was completely received while the RxFIFO
was full, and this interrupt is enabled.
This bit is 1 if the Rx FIFO is not empty, has not been read for a
"timeout period", and this interrupt is enabled. The timeout period is the
same for master and slave modes and is determined by the SSP bit
rate: 32 bits at PCLK / (CPSDVSR × [SCR+1]).
This bit is 1 if the Rx FIFO is at least half full, and this interrupt is
enabled.
This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is
enabled.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 2 — 19 August 2010
Chapter 18: LPC17xx SSP0/1
UM10360
© NXP B.V. 2010. All rights reserved.
426 of 840
Reset
Value
0
0
0
0
NA
Reset
Value
NA
NA
NA
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