LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 9
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
1.6 Architectural overview
1.7 ARM Cortex-M3 processor
UM10360
User manual
1.7.1 Cortex-M3 Configuration Options
The ARM Cortex-M3 includes three AHB-Lite buses, one system bus and the I-code and
D-code buses which are faster and are used similarly to TCM interfaces: one bus
dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of
two core buses allows for simultaneous operations if concurrent operations target different
devices.
The LPC17xx uses a multi-layer AHB matrix to connect the Cortex-M3 buses and other
bus masters to peripherals in a flexible manner that optimizes performance by allowing
peripherals on different slaves ports of the matrix to be accessed simultaneously by
different bus masters. Details of the multilayer matrix connections are shown in
APB peripherals are connected to the CPU via two APB busses using separate slave
ports from the multilayer AHB matrix. This allows for better performance by reducing
collisions between the CPU and the DMA controller. The APB bus bridges are configured
to buffer writes so that the CPU or DMA controller can write to APB devices without
always waiting for APB write completion.
The ARM Cortex-M3 is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The Cortex-M3 offers many new features,
including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptible/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with Wakeup Interrupt
Controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 User Guide that is
appended to this manual.
The LPC17xx uses the r2p0 version of the Cortex-M3 CPU, which includes a number of
configurable options, as noted below.
System options:
•
•
•
•
The Nested Vectored Interrupt Controller (NVIC) is included. The NVIC includes the
SYSTICK timer.
The Wakeup Interrupt Controller (WIC) is included. The WIC allows more powerful
options for waking up the CPU from reduced power modes.
A Memory Protection Unit (MPU) is included.
A ROM Table in included. The ROM Table provides addresses of debug components
to external debug systems.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 1: LPC17xx Introductory information
UM10360
© NXP B.V. 2010. All rights reserved.
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