LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 39

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
4.5.5 PLL0 Status register (PLL0STAT - 0x400F C088)
4.5.6 PLL0 Interrupt: PLOCK0
The read-only PLL0STAT register provides the actual PLL0 parameters that are in effect
at the time it is read, as well as PLL0 status. PLL0STAT may disagree with values found in
PLL0CON and PLL0CFG because changes to those registers do not take effect until a
proper PLL0 feed has occurred (see
0x400F
Table 22.
The PLOCK0 bit in the PLL0STAT register reflects the lock status of PLL0. When PLL0 is
enabled, or parameters are changed, PLL0 requires some time to establish lock under the
new conditions. PLOCK0 can be monitored to determine when PLL0 may be connected
for use. The value of PLOCK0 may not be stable when the PLL reference frequency
(F
pre-divider value) is less than 100 kHz or greater than 20 MHz. In these cases, the PLL
may be assumed to be stable after a start-up time has passed. This time is 500 μs when
FREF is greater than 400 kHz and 200 / FREF seconds when FREF is less than 400 kHz
PLOCK0 is connected to the interrupt controller. This allows for software to turn on PLL0
and continue with other functions without having to wait for PLL0 to achieve lock. When
the interrupt occurs, PLL0 may be connected, and the interrupt disabled. PLOCK0
appears as interrupt 32 in
is locked, so if the interrupt is used, the interrupt service routine must disable the PLOCK0
interrupt prior to exiting.
Bit
14:0
15
23:16 NSEL0
24
25
26
31:27 -
REF
, the frequency of REFCLK, which is equal to the PLL input frequency divided by the
Symbol
MSEL0
-
PLLE0_STAT Read-back for the PLL0 Enable bit. This bit reflects the state of the
PLLC0_STAT Read-back for the PLL0 Connect bit. This bit reflects the state of
PLOCK0
C08C)”).
PLL Status register (PLL0STAT - address 0x400F C088) bit description
All information provided in this document is subject to legal disclaimers.
Description
Read-back for the PLL0 Multiplier value. This is the value currently
used by PLL0, and is one less than the actual multiplier.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Read-back for the PLL0 Pre-Divider value. This is the value
currently used by PLL0, and is one less than the actual divider.
PLEC0 bit in PLL0CON (see
When one, PLL0 is currently enabled. When zero, PLL0 is turned
off. This bit is automatically cleared when Power-down mode is
entered.
the PLLC0 bit in PLL0CON (see
When PLLC0 and PLLE0 are both one, PLL0 is connected as the
clock source for the CPU. When either PLLC0 or PLLE0 is zero,
PLL0 is bypassed. This bit is automatically cleared when
Power-down mode is entered.
Reflects the PLL0 Lock status. When zero, PLL0 is not locked.
When one, PLL0 is locked onto the requested frequency. See text
for details.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 2 — 19 August 2010
Table
50. Note that PLOCK0 remains asserted whenever PLL0
Section 4.5.8 “PLL0 Feed register (PLL0FEED -
Chapter 4: LPC17xx Clocking and power control
Table
Table
19) after a valid PLL0 feed.
19) after a valid PLL0 feed.
UM10360
© NXP B.V. 2010. All rights reserved.
39 of 840
Reset
value
0
NA
0
0
0
0
NA