LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 153

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 134. Collision Window / Retry register (CLRT - address 0x5000 0010) bit description
Table 135. Maximum Frame register (MAXF - address 0x5000 0014) bit description
Table 136. PHY Support register (SUPP - address 0x5000 0018) bit description
UM10360
User manual
Bit
3:0
7:4
13:8
31:14 -
Bit
15:0
31:16
Bit
7:0
8
31:9
Symbol
RETRANSMISSION
MAXIMUM
-
COLLISION
WINDOW
Symbol
-
SPEED
-
Symbol
MAXIMUM FRAME
LENGTH
-
10.11.5 Collision Window / Retry Register (CLRT - 0x5000 0010)
10.11.6 Maximum Frame Register (MAXF - 0x5000 0014)
10.11.7 PHY Support Register (SUPP - 0x5000 0018)
10.11.8 Test Register (TEST - 0x5000 001C)
The Collision window / Retry register (CLRT) has an address of 0x5000 0010. Its bit
definition is shown in
The Maximum Frame register (MAXF) has an address of 0x5000 0014. Its bit definition is
shown in
The PHY Support register (SUPP) has an address of 0x5000 0018. The SUPP register
provides additional control over the RMII interface. The bit definition of this register is
shown in
Unused bits in the PHY support register should be left as zeroes.
The Test register (TEST) has an address of 0x5000 001C. The bit definition of this register
is shown in
Function
This field resets to the value 0x0600, which represents a maximum receive frame of
1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged
frame adds four octets for a total of 1522 octets. If a shorter maximum length
restriction is desired, program this 16-bit field.
Unused
Function
This is a programmable field specifying the number of retransmission attempts
following a collision before aborting the packet due to excessive collisions. The
Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5.
Reserved. User software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
This is a programmable field representing the slot time or collision window during
which collisions occur in properly configured networks. The default value of 0x37
(55d) represents a 56 byte window following the preamble and SFD.
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
Function
Unused
This bit configures the Reduced MII logic for the current operating speed. When set,
100 Mbps mode is selected. When cleared, 10 Mbps mode is selected.
Unused
Table
Table
Table
135.
136.
All information provided in this document is subject to legal disclaimers.
137. These bits are used for testing purposes only.
Table
Rev. 2 — 19 August 2010
134.
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
153 of 840
Reset
value
0x0600
0x0
Reset
value
0xF
0x0
0x37
NA
Reset
value
0x0
0
0x0