LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 142

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
10.3 Features
UM10360
User manual
Table 124. Ethernet acronyms, abbreviations, and definitions
Acronym or
Abbreviation
Frame
Half-word
LAN
MAC
MII
MIIM
Octet
Packet
PHY
RMII
Rx
TCP/IP
Tx
VLAN
WoL
Word
•
•
•
Ethernet standards support:
– Supports 10 or 100 Mbps PHY devices including 10 Base-T, 100 Base-TX,
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
– Flexible transmit and receive frame options.
– VLAN frame support.
Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and prefetching.
Enhanced Ethernet features:
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic FCS insertion (CRC) for transmit.
– Selectable automatic transmit frame padding.
100 Base-FX, and 100 Base-T4.
pressure.
All information provided in this document is subject to legal disclaimers.
Definition
An Ethernet frame consists of destination address, source address, length
type field, payload and frame check sequence.
16-bit entity
Local Area Network
Media Access Control sublayer
Media Independent Interface
MII management
An 8-bit data entity, used in lieu of "byte" by IEEE 802.3
A frame that is transported across Ethernet; a packet consists of a preamble,
a start of frame delimiter and an Ethernet frame.
Ethernet Physical Layer
Reduced MII
Receive
Transmission Control Protocol / Internet Protocol. The most common
high-level protocol used with Ethernet.
Transmit
Virtual LAN
Wake-up on LAN
32-bit entity
Rev. 2 — 19 August 2010
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
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