LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 322

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 292: UART1 Divisor Latch LSB Register (U1DLL - address 0x4001 0000 when DLAB = 1) bit description
Table 293: UART1 Divisor Latch MSB Register (U1DLM - address 0x4001 0004 when DLAB = 1) bit description
Table 294: UART1 Interrupt Enable Register (U1IER - address 0x4001 0004 when DLAB = 0) bit description
UM10360
User manual
Bit
7:0
31:8
Bit
7:0
31:8
Bit
0
1
2
3
6:4
7
Symbol Description
DLLSB
-
Symbol Description
DLMSB
-
Symbol
RBR
Interrupt
Enable
THRE
Interrupt
Enable
RX Line
Interrupt
Enable
Modem
Status
Interrupt
Enable
-
CTS
Interrupt
Enable
15.4.4 UART1 Interrupt Enable Register (U1IER - 0x4001 0004, when
The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the
baud rate of the UART1.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the
baud rate of the UART1.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Value Description
0
1
0
1
0
1
0
1
0
1
DLAB = 0)
The U1IER is used to enable the four UART1 interrupt sources.
enables the Receive Data Available interrupt for UART1. It also controls the Character
Receive Time-out interrupt.
Disable the RDA interrupts.
Enable the RDA interrupts.
enables the THRE interrupt for UART1. The status of this interrupt can be read from
U1LSR[5].
Disable the THRE interrupts.
Enable the THRE interrupts.
enables the UART1 RX line status interrupts. The status of this interrupt can be read
from U1LSR[4:1].
Disable the RX line status interrupts.
Enable the RX line status interrupts.
enables the modem interrupt. The status of this interrupt can be read from U1MSR[3:0]. 0
Disable the modem interrupt.
Enable the modem interrupt.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
If auto-cts mode is enabled this bit enables/disables the modem status interrupt
generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition
will generate an interrupt if Modem Status Interrupt Enable (U1IER[3]) is set.
In normal operation a CTS1 signal transition will generate a Modem Status Interrupt
unless the interrupt has been disabled by clearing the U1IER[3] bit in the U1IER
register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both
the U1IER[3] and U1IER[7] bits are set.
Disable the CTS interrupt.
Enable the CTS interrupt.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 15: LPC17xx UART1
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
0x01
NA
Reset Value
0x00
NA
322 of 840
Reset
Value
0
0
0
NA
0