LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 191
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
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UM10360
User manual
receive errors cannot be reported in the receiver Status arrays which corrupts the
hardware state; the errors will still be reported in the IntStatus register’s Overrun bit. The
RxReset bit in the Command register should be used to soft reset the hardware.
Device drivers should catch the above receive errors and take action.
Receive triggers interrupts
The receive data path can generate four different interrupt types:
All of the above interrupts can be enabled and disabled by setting or resetting the
corresponding bits in the IntEnable register. Enabling or disabling does not affect the
IntStatus register contents, only the propagation of the interrupt status to the CPU (via the
NVIC).
The interrupts, either of individual frames or of the whole list, are a good means of
communication between the DMA manager and the device driver, triggering the device
driver to inspect the status words of descriptors that have been processed.
Device driver processes receive data
As a response to status (e.g. RxDoneInt) interrupts or polling of the RxProduceIndex, the
device driver can read the descriptors that have been handed over to it by the hardware
(RxProduceIndex - RxConsumeIndex). The device driver should inspect the status words
in the status array to check for multi-fragment receptions and receive errors.
The device driver can forward receive data and status to upper software layers. After
processing of data and status, the descriptors, statuses and data buffers may be recycled
and handed back to hardware by incrementing the RxConsumeIndex.
Receive example
Figure 22
•
•
•
•
If the Interrupt bit in the descriptor Control field is set, the Rx DMA will set the
RxDoneInt bit in the IntStatus register after receiving a fragment and committing the
associated data and status to memory. Even if a descriptor (fragment) is not the last in
a multi-fragment frame, the Interrupt bit in the descriptor can be used to generate an
interrupt.
If the descriptor array is full while the Ethernet hardware is enabled, the hardware will
set the RxFinishedInt bit of the IntStatus register.
If the AHB interface does not consume receive statuses at a sufficiently high
bandwidth, the receive status process may overrun, in which case the RxOverrun bit
will be set in the IntStatus register.
If there is a receive error (AlignmentError, RangeError, LengthError, SymbolError, or
CRCError), or a multi-fragment frame where the device driver did provide descriptors
for the initial fragments but did not provide the descriptors for the rest of the
fragments, or if a nonfatal data Overrun occurred, the hardware will set the RxErrorInt
bit of the IntStatus register.
illustrates the receive process in an example receiving a frame of 19 bytes.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 19 August 2010
Chapter 10: LPC17xx Ethernet
UM10360
© NXP B.V. 2010. All rights reserved.
191 of 840
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