LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 156

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
10.11.13 MII Mgmt Read Data Register (MRDD - 0x5000 0030)
10.11.14 MII Mgmt Indicators Register (MIND - 0x5000 0034)
Table 142. MII Mgmt Write Data register (MWTD - address 0x5000 002C) bit description
The MII Mgmt Read Data register (MRDD) is a read-only register with an address of
0x5000 0030. The bit definition of this register is shown in
Table 143. MII Mgmt Read Data register (MRDD - address 0x5000 0030) bit description
The MII Mgmt Indicators register (MIND) is a read-only register with an address of
0x5000 0034. The bit definition of this register is shown in
Table 144. MII Mgmt Indicators register (MIND - address 0x5000 0034) bit description
Here are two examples to access PHY via the MII Management Controller.
For PHY Write if scan is not used:
For PHY Read if scan is not used:
Bit
15:0
31:16 -
Bit
15:0
31:16 -
Bit
0
1
2
3
31:4
1. Write 0 to MCMD
2. Write PHY address and register address to MADR
3. Write data to MWTD
4. Wait for busy bit to be cleared in MIND
1. Write 1 to MCMD
2. Write PHY address and register address to MADR
Symbol
WRITE
DATA
Symbol
READ
DATA
Symbol
BUSY
SCANNING When ’1’ is returned - indicates a scan operation (continuous MII
NOT VALID
MII Link Fail When ’1’ is returned - indicates that an MII Mgmt link fail has
-
All information provided in this document is subject to legal disclaimers.
Function
Following an MII Mgmt Read Cycle, the 16-bit data can be read from
this location.
Unused
Function
When written, an MII Mgmt write cycle is performed using the 16-bit
data and the pre-configured PHY and Register addresses from the
MII Mgmt Address register (MADR).
Unused
Function
When ’1’ is returned - indicates MII Mgmt is currently performing an
MII Mgmt Read or Write cycle.
Mgmt Read cycles) is in progress.
When ’1’ is returned - indicates MII Mgmt Read cycle has not
completed and the Read Data is not yet valid.
occurred.
Unused
Rev. 2 — 19 August 2010
Chapter 10: LPC17xx Ethernet
Table
Table
143.
144.
UM10360
© NXP B.V. 2010. All rights reserved.
156 of 840
Reset
value
0x0
0x0
Reset
value
0x0
0x0
Reset
value
0
0
0
0
0x0