LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 792

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
UM10360
User manual
34.4.5.6 MPU access permission attributes
This section describes the MPU access permission attributes. The access permission
bits, TEX, C, B, S, AP, and XN, of the RASR, control access to the corresponding memory
region. If an access is made to an area of memory without the required permissions, then
the MPU generates a permission fault.
Table 687
Table 687. TEX, C, B, and S encoding
[1]
[2]
Table 688
the range 4-7.
Table 688. Cache policy for memory attribute encoding
Table 689
unprivileged software.
TEX
b000
b001
b010
b1BB
Encoding, AA or BB
00
01
10
11
The MPU ignores the value of this bit.
See
Table 688
C
0
1
0
1
0
1
A
shows the encodings for the TEX, C, B, and S access permission bits.
shows the cache policy for memory attribute encodings with a TEX value is in
shows the AP encodings that define the access permissions for privileged and
B
0
1
0
1
0
1
0
1
0
1
x
A
All information provided in this document is subject to legal disclaimers.
for the encoding of the AA and BB bits.
[1]
S
x
x
0
1
0
1
0
1
x
x
0
1
x
x
x
0
1
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Rev. 2 — 19 August 2010
Memory type
Strongly-ordered
Device
Normal
Normal
Normal
Reserved encoding
Implementation defined attributes.
Normal
Device
Reserved encoding
Reserved encoding
Normal
Chapter 34: Appendix: Cortex-M3 user guide
Shareability
Shareable
Shareable
Not shareable
Shareable
Not shareable
Shareable
Not shareable
Shareable
Not shareable
Shareable
Not shareable
Not shareable
Shareable
Corresponding cache policy
Non-cacheable
Write back, write and read allocate
Write through, no write allocate
Write back, no write allocate
Other attributes
-
-
Outer and inner write-through.
No write allocate.
Outer and inner write-back. No
write allocate.
Outer and inner noncacheable.
-
-
Outer and inner write-back. Write
and read allocate.
Nonshared Device.
-
-
Cached memory
policy, AA = inner policy.
UM10360
© NXP B.V. 2010. All rights reserved.
[2]
, BB = outer
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