LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 609

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 566. DMA request signal usage
UM10360
User manual
Transfer direction
Memory-to-peripheral
Peripheral-to-memory
Memory-to-memory
Source peripheral to destination peripheral
31.6.2.1 Peripheral-to-memory or memory-to-peripheral DMA flow
31.6.2.2 Peripheral-to-peripheral DMA flow
For a peripheral-to-memory or memory-to-peripheral DMA flow, the following sequence
occurs:
For a peripheral-to-peripheral DMA flow, the following sequence occurs:
1. Program and enable the DMA channel.
2. Wait for a DMA request.
3. The DMA Controller starts transferring data when:
4. If an error occurs while transferring the data, an error interrupt is generated and
5. Decrement the transfer count.
6. If the transfer has completed (indicated by the transfer count reaching 0):
1. Program and enable the DMA channel.
2. Wait for a source DMA request.
3. The DMA Controller starts transferring data when:
4. If an error occurs while transferring the data an error interrupt is generated, the DMA
5. Decrement the transfer count.
6. If the transfer has completed (indicated by the transfer count reaching 0):
– The DMA request goes active.
– The DMA stream has the highest pending priority.
– The DMA Controller is the bus master of the AHB bus.
disables the DMA stream, and the flow sequence ends.
– The DMA Controller responds with a DMA acknowledge.
– The terminal count interrupt is generated (this interrupt can be masked).
– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr,
– The DMA request goes active.
– The DMA stream has the highest pending priority.
– The DMA Controller is the bus master of the AHB bus.
stream is disabled, and the flow sequence ends.
– The DMA Controller responds with a DMA acknowledge to the source peripheral.
– Further source DMA requests are ignored.
DMACCxDestAddr, DMACCxLLI, and DMACCxControl registers and go to back to
step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow
sequence ends.
All information provided in this document is subject to legal disclaimers.
Request generator
Peripheral
Peripheral
DMA Controller
Source peripheral and destination peripheral
Rev. 2 — 19 August 2010
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
DMA Controller
DMA Controller
DMA Controller
DMA Controller
Flow controller
UM10360
© NXP B.V. 2010. All rights reserved.
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