LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 596

• Manufacturer Part Number: LPC1769FBD100,551
• Description: IC ARM CORTEX MCU 512K 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1769FBD100,551

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-LQFP
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 120MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 70
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC17
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: Ethernet, USB, OTG, CAN
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• On-chip Dac: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4966; 935290522551

NXP Semiconductors
Table 548. DMA Interrupt Error Status register (DMACIntErrStat - 0x5000 400C)
Table 549. DMA Interrupt Error Clear register (DMACIntErrClr - 0x5000 4010)
Table 550. DMA Raw Interrupt Terminal Count Status register (DMACRawIntTCStat - 0x5000 4014)
UM10360
User manual
Bit
7:0
31:8
Bit
7:0
31:8
Bit
7:0
31:8
Name
IntErrStat
-
Name
IntErrClr
-
Name
RawIntTCStat
-
31.5.5 DMA Interrupt Error Clear register (DMACIntErrClr - 0x5000 4010)
31.5.6 DMA Raw Interrupt Terminal Count Status register
31.5.7 DMA Raw Error Interrupt Status register (DMACRawIntErrStat -
The DMACIntErrClr Register is write-only and clears the error interrupt requests. When
writing to this register, each data bit that is 1 causes the corresponding bit in the status
register to be cleared. Data bits that are 0 have no effect on the corresponding bit in the
register.
(DMACRawIntTCStat - 0x5000 4014)
The DMACRawIntTCStat Register is read-only and indicates which DMA channel is
requesting a transfer complete (terminal count interrupt) prior to masking. (Note: the
DMACIntTCStat Register contains the same information after masking.) A 1 bit indicates
that the terminal count interrupt request is active prior to masking.
assignments of the DMACRawIntTCStat Register.
0x5000 4018)
The DMACRawIntErrStat Register is read-only and indicates which DMA channel is
requesting an error interrupt prior to masking. (Note: the DMACIntErrStat Register
contains the same information after masking.) A 1 bit indicates that the error interrupt
request is active prior to masking.
DMACRawIntErrStat Register.
Table 549
Function
Interrupt error status for DMA channels. Each bit represents one channel:
0 - the corresponding channel has no active error interrupt request.
1 - the corresponding channel does have an active error interrupt request.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Function
Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit
represents one channel:
0 - writing 0 has no effect.
1 - clears the corresponding channel error interrupt.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Function
Status of the terminal count interrupt for DMA channels prior to masking. Each bit
represents one channel:
0 - the corresponding channel has no active terminal count interrupt request.
1 - the corresponding channel does have an active terminal count interrupt request.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
shows the bit assignments of the DMACIntErrClr Register.
Rev. 2 — 19 August 2010
Chapter 31: LPC17xx General Purpose DMA (GPDMA)
Table 551
shows the bit assignments of register of the
Table 550
UM10360
© NXP B.V. 2010. All rights reserved.
shows the bit
596 of 840