LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 104
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
NXP Semiconductors
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10 000
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6. MAM configuration
UM10237_4
User manual
Table 96.
[1]
[2]
Table 97.
[1]
After reset the MAM defaults to the disabled state. Software can turn memory access
acceleration on or off at any time. This allows most of an application to be run at the
highest possible performance, while certain functions can be run at a somewhat slower
but more predictable rate if more precise timing is required.
Program Memory Request Type
Sequential access, data in latches
Sequential access, data not in latches
Non-sequential access, data in latches
Non-sequential access, data not in
latches
Data Memory Request Type
Sequential access, data in latches
Sequential access, data not in latches
Non-sequential access, data in latches
Non-sequential access, data not in latches Initiate Fetch
Mode 1: MAM partially enabled. Sequential instruction accesses are fulfilled from the
holding latches if the data is present. Instruction prefetch is enabled. Non-sequential
instruction accesses initiate Flash read operations (see
that all branches cause memory fetches. All data operations cause a Flash read
because buffered data access timing is hard to predict and is very situation dependent.
Mode 2: MAM fully enabled. Any memory request (code or data) for a value that is
contained in one of the corresponding holding latches is fulfilled from the latch.
Instruction prefetch is enabled. Flash read operations are initiated for instruction
prefetch and code or data values not available in the corresponding holding latches.
Instruction prefetch is enabled in modes 1 and 2.
The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
MAM responses to program accesses of various types
MAM responses to data and DMA accesses of various types
Rev. 04 — 26 August 2009
Chapter 6: LPC24XX Memory Accelerator Module (MAM)
MAM Mode
0
Initiate Fetch
Initiate Fetch
Initiate Fetch
Initiate Fetch
MAM Mode
0
Initiate Fetch
Initiate Fetch
Initiate Fetch
[2]
[2]
[1]
[1]
1
Use Latched
Data
Initiate Fetch
Initiate Fetch
Initiate Fetch
Initiate Fetch
1
Initiate Fetch
Initiate Fetch
Initiate Fetch
Table note
[1]
[1]
[1][2]
[1]
[1]
[1]
6–2). This means
UM10237
© NXP B.V. 2009. All rights reserved.
2
Use Latched
Data
Initiate Fetch
Use Latched
Data
Initiate Fetch
2
Use Latched
Data
Initiate Fetch
Use Latched
Data
Initiate Fetch
[1]
[1]
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[1]
[1]
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