LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 356

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
9.8.6 USB EP DMA Enable register (USBEpDMAEn - 0xFFE0 C288)
9.8.7 USB EP DMA Disable register (USBEpDMADis - 0xFFE0 C28C)
9.8.8 USB DMA Interrupt Status register (USBDMAIntSt - 0xFFE0 C290)
Writing one to a bit to this register will enable the DMA operation for the corresponding
endpoint. Writing zero has no effect.The DMA cannot be enabled for control endpoints
EP0 and EP1. USBEpDMAEn is a write only register.
Table 334. USB EP DMA Enable register (USBEpDMAEn - address 0xFFE0 C288) bit
Writing a one to a bit in this register clears the corresponding bit in USBEpDMASt. Writing
zero has no effect on the corresponding bit of USBEpDMASt. Any write to this register
clears the internal DMA_PROCEED flag. Refer to
descriptor fetch”
progress for an endpoint when its corresponding bit is cleared, the transfer is completed
before the DMA is disabled. When an error condition is detected during a DMA transfer,
the corresponding bit is cleared by hardware. USBEpDMADis is a write only register.
Table 335. USB EP DMA Disable register (USBEpDMADis - address 0xFFE0 C28C) bit
Each bit of this register reflects whether any of the 32 bits in the corresponding interrupt
status register are set. USBDMAIntSt is a read only register.
Bit
0
1
31:2 EPxx_DMA_ENABLE
Bit
0
1
31:2 EPxx_DMA_DISABLE
Symbol
EP0_DMA_ENABLE
EP1_DMA_ENABLE
Symbol
EP0_DMA_DISABLE
EP1_DMA_DISABLE
description
description
for more information on the DMA_PROCEED flag. If a DMA transfer is in
Rev. 04 — 26 August 2009
Value Description
0
0
0
1
Value Description
0
0
0
1
Control endpoint OUT (DMA cannot be enabled for
this endpoint and the EP0_DMA_ENABLE bit value
must be 0).
Control endpoint IN (DMA cannot be enabled for this
endpoint and the EP1_DMA_ENABLE bit must be 0).
Endpoint xx(2 ≤ xx ≤ 31) DMA enable control bit.
No effect.
Enable the DMA operation for endpoint EPxx.
Control endpoint OUT (DMA cannot be enabled for
this endpoint and the EP0_DMA_DISABLE bit value
must be 0).
Control endpoint IN (DMA cannot be enabled for
this endpoint and the EP1_DMA_DISABLE bit value
must be 0).
Endpoint xx (2 ≤ xx ≤ 31) DMA disable control bit.
No effect.
Disable the DMA operation for endpoint EPxx.
Chapter 13: LPC24XX USB device controller
Section 13–14.5.4 “Optimizing
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
value
0
0
0
Reset
value
0
0
0