LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 558

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
Fig 109. Data path state machine
FIFO underrun or
end of data or
Disabled or
CRC fail
End of packet
BUSY
The DPSM moves to the RECEIVE state if it receives a start bit before a timeout, and
loads the data block counter. If it reaches a timeout before it detects a start bit, or a start
bit error occurs, it moves to the IDLE state and sets the timeout status flag.
If a FIFO overrun error occurs, the DPSM sets the FIFO error flag and moves to the
WAIT_R state.
•
•
•
SEND
IDLE: The data path is inactive, and the MCIDAT[3:0] outputs are in HI-Z. When the
data control register is written and the enable bit is set, the DPSM loads the data
counter with a new value and, depending on the data direction bit, moves to either the
WAIT_S or WAIT_R state.
WAIT_R: If the data counter equals zero, the DPSM moves to the IDLE state when
the receive FIFO is empty. If the data counter is not zero, the DPSM waits for a start
bit on MCIDAT.
RECEIVE: Serial data received from a card is packed in bytes and written to the data
FIFO. Depending on the transfer mode bit in the data control register, the data transfer
mode can be either block or stream:
– In block mode, when the data block counter reaches zero, the DPSM waits until it
– In stream mode, the DPSM receives data while the data counter is not zero. When
WAIT_S: The DPSM moves to the IDLE state if the data counter is zero. If not, it waits
until the data FIFO empty flag is deasserted, and moves to the SEND state.
receives the CRC code. If the received code matches the internally generated
CRC code, the DPSM moves to the WAIT_R state. If not, the CRC fail status flag is
set and the DPSM moves to the IDLE state.
the counter is zero, the remaining data in the shift register is written to the data
FIFO, and the DPSM moves to the WAIT_R state.
Not busy
Disabled or
CRC fail or
timeout
Data ready
Disabled or
end of data
WAIT_S
Rev. 04 — 26 August 2009
and send
Enable
IDLE
Rx FIFO empty
or timeout or
start bit error
Disabled or
Chapter 21: LPC24XX SD/MMC card interface
Start bit
Enable and
not send
WAIT_R
Reset
or FIFO overrun
End of packet
or end of data
RECEIVE
Disabled or
CRC fail
UM10237
© NXP B.V. 2009. All rights reserved.
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