LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 616

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
5.6 DMA Configuration Register 1 (I2SDMA1 - 0xE008 8014)
5.7 DMA Configuration Register 2 (I2SDMA2 - 0xE008 8018)
5.8 Interrupt Request Control Register (I2SIRQ - 0xE008 801C)
Table 536: Status Feedback register (I2SSTATE - address 0xE008 8010) bit description
The I2SDMA1 register controls the operation of DMA request 1. The function of bits in
I2SDMA1 are shown in
chapter for details of DMA operation.
Table 537: DMA Configuration register 1 (I2SDMA1 - address 0xE008 8014) bit description
The I2SDMA2 register controls the operation of DMA request 2. The function of bits in
I2SDMA2 are shown in
Table 538: DMA Configuration register 2 (I2SDMA2 - address 0xE008 8018) bit description
The I2SIRQ register controls the operation of the I
in I2SIRQ are shown in
Bit
15:8
23:16 tx_level
31:24 -
Bit
0
1
7:2
15:8
23:16
31:24
Bit
0
1
7:2
15:8
23:16
31:24
Symbol
rx_level
Symbol
rx_dma2_enable
tx_dma2_enable
Unused
rx_depth_dma2
tx_depth_dma2
-
Symbol
rx_dma1_enable
tx_dma1_enable
Unused
rx_depth_dma1
tx_depth_dma1
-
Description
Reflects the current level of the Receive FIFO.
Reflects the current level of the Transmit FIFO.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 04 — 26 August 2009
Table
Table
Table
Description
When 1, enables DMA1 for I
When 1, enables DMA1 for I
Unused.
Set the FIFO level that triggers a receive DMA request on
DMA1.
Set the FIFO level that triggers a transmit DMA request on
DMA1.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
When 1, enables DMA1 for I
When 1, enables DMA1 for I
Unused.
Set the FIFO level that triggers a receive DMA request
on DMA2.
Set the FIFO level that triggers a transmit DMA request
on DMA2.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
23–537. Refer to the General Purpose DMA Controller
23–532.
23–532.
2
S interrupt request. The function of bits
Chapter 23: LPC24XX I
2
2
S receive.
S transmit.
2
2
S receive.
S transmit.
UM10237
© NXP B.V. 2009. All rights reserved.
2
S interface
Reset
Value
0
0
0
0
0
NA
616 of 792
0
0
Reset
Value
NA
Reset
Value
0
0
0
0
0
NA