LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 697

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

1. How to read this chapter
2. Features
3. Applications
4. Description
UM10237_4
User manual
Remark: This chapter describes the boot process for flashless parts LPC2420/60 and
LPC2470. It does not apply to parts LPC2458, LPC2468, and LPC2478.
The on-chip bootloader version 3.4 controls the boot process for flashless LPC2400 parts
LPC2420/60 and LPC2470.
The boot loader provides both In-System and In-Application programming interfaces for
programming the on-chip memory.
The bootloader is designed as a tool that enables the user to load system specific
application for further programming of in system available off-chip Flash and/or RAM
resources. The bootloader itself does not contain any external memory programming
algorithms. The bootloader implemented in LPC2460/70 supports a limited set of
commands dedicated to code download and its execution from on-chip RAM only. UART0
is the sole serial channel the boot loader can use for data download. Although a fractional
divider is available in the UART0, it is not used by the on-chip bootloader.
The boot loader code is executed every time the part is powered on or reset. The loader
can execute the ISP command handler or the user application code. A LOW level after
reset at the P2.10 pin is considered as an external hardware request to start the ISP
command handler. Assuming that power supply pins are on their nominal levels when the
rising edge on RESET pin is generated, it may take up to 3 ms before P2.10 is sampled
and the decision on whether to continue with user code or ISP handler is made. If P2.10 is
sampled low and the watchdog overflow flag is set, the external hardware request to start
the ISP command handler is ignored. If there is no request for the ISP command handler
execution (P2.10 is sampled HIGH after reset), a search is made for a valid user program.
If a valid user program is found then the execution control is transferred to it. If a valid user
program is not found, the auto-baud routine is invoked.
•
•
UM10237
Chapter 31: LPC24XX On-chip bootloader for flashless parts
Rev. 04 — 26 August 2009
In-System Programming: In-System programming (ISP) is programming or
reprogramming the on-chip memory, using the boot loader software and UART0 serial
port. This can be done when the part resides in the end-user board.
In Application Programming: In-Application (IAP) programming is performing erase
and write operation on the on-chip memory, as directed by the end-user application
code.
Rev. 04 — 26 August 2009
© NXP B.V. 2009. All rights reserved.
User manual
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