LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 733

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
7. Address generation
8. Scatter/Gather
UM10237_4
User manual
6.2.8 Flow control and transfer type
8.1 Linked List Items
There are situations when the GPDMA asserts the lock for source transfers followed by
destination transfers. This is possible when internal conditions in the GPDMA permit it to
perform a source fetch followed by a destination drain back-to-back.
Table 32–675
Table 675. Flow control and transfer type bits
Address generation can be either incrementing or non-incrementing (address wrapping is
not supported). Bursts do not cross the 1 kB address boundary.
Scatter/gather is supported through the use of linked lists. This means that the source and
destination areas do not have to occupy contiguous areas in memory. Where
scatter/gather is not required the DMACCxLLI Register must be set to 0.
The source and destination data areas are defined by a series of linked lists. Each Linked
List Item (LLI) controls the transfer of one block of data, and then optionally loads another
LLI to continue the DMA operation, or stops the DMA stream. The first LLI is programmed
into the GPDMA.
The data to be transferred described by a LLI (referred to as the packet of data) usually
requires one or more DMA bursts (to each of the source and destination).
A Linked List Item (LLI) consists of four words. These words are organized in the following
order:
Note: The DMACCxConfiguration DMA channel Configuration Register is not part of the
linked list item.
Bit Value Transfer Type
000
001
010
011
100
101
110
111
1. DMACCxSrcAddr.
2. DMACCxDestAddr.
3. DMACCxLLI.
4. DMACCxControl.
Memory to memory.
Memory to peripheral.
Peripheral to memory.
Source peripheral to destination peripheral.
Source peripheral to destination peripheral.
Memory to peripheral.
Peripheral to memory.
Source peripheral to destination peripheral.
lists the bit values of the three flow control and transfer type bits.
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
Controller
DMA
DMA
DMA
DMA
Destination peripheral.
Peripheral.
Peripheral.
Source peripheral.
UM10237
© NXP B.V. 2009. All rights reserved.
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