LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 241

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
8. Descriptor and status formats
UM10237_4
User manual
7.4.5 Power-Down Register (PowerDown - 0xFFE0 0FF4)
8.1 Receive descriptors and statuses
Table 231. Interrupt Set register (IntSet - address 0xFFE0 0FEC) bit description
The interrupt set register is write-only. Writing a 1 to a bit of the IntSet register sets the
corresponding bit in the status register. Writing a 0 will not affect the interrupt status.
The Power-Down register (PowerDown) is used to block all AHB accesses except
accesses to the PowerDown register. The register has an address of 0xFFE0 0FF4. The
bit definition of the register is listed in
Table 232. Power-Down register (PowerDown - address 0xFFE0 0FF4) bit description
Setting the bit will return an error on all read and write accesses on the MACAHB interface
except for accesses to the PowerDown register.
This section defines the descriptor format for the transmit and receive scatter/gather DMA
engines. Each Ethernet frame can consist of one or more fragments. Each fragment
corresponds to a single descriptor. The DMA managers in the Ethernet block scatter (for
receive) and gather (for transmit) multiple fragments for a single Ethernet frame.
Figure 11–28
Bit
0
1
2
3
4
5
6
7
11:8
12
13
31:14
Bit
30:0
31
Symbol
RxOverrunIntSet
RxErrorIntSet
RxFinishedIntSet
RxDoneIntSet
TxUnderrunIntSet
TxErrorIntSet
TxFinishedIntSet
TxDoneIntSet
-
SoftIntSet
WakeupIntSet
-
Symbol
-
PowerDownMACAHB
depicts the layout of the receive descriptors in memory.
Rev. 04 — 26 August 2009
Function
Writing a ’1’ to one of these bits (0 to 7) sets the
corresponding status bit in interrupt status register
IntStatus.
Unused
Writing a ’1’ to one of these bits (12 and/or 13) sets the
corresponding status bit in interrupt status register
IntStatus.
Unused
Function
Unused
If true, all AHB accesses will return a read/write error,
except accesses to the PowerDown register.
Table
11–232.
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
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Reset
value
0x0
0
0
Reset
value
0
0
0
0
0
0
0
0x0
0
0
0x0