LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 487
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Table 427. Status Register (CAN1SR - address 0xE004 401C, CAN2SR - address 0xE004 801C) bit description
UM10237_4
User manual
Bit
0
1
2
3
4
Symbol Value
RBS
DOS
TBS1
TCS1
RS
[1]
[2]
0(locked)
1(released)
0(incomplete) The previously requested transmission for Tx Buffer 1 is not complete.
1(complete)
8.7 Error Warning Limit Register (CAN1EWL - 0xE004 4018, CAN2EWL -
8.8 Status Register (CAN1SR - 0xE004 401C, CAN2SR - 0xE004 801C)
0xE004 8018)
This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be read
at any time but can only be written if the RM bit in CANmod is 1. The default value (after
hardware reset) is 96.
Table 426. Error Warning Limit register (CAN1EWL - address 0xE004 4018, CAN2EWL -
Note that a content change of the Error Warning Limit Register is possible only if the
Reset Mode was entered previously. An Error Status change (Status Register) and an
Error Warning Interrupt forced by the new register content will not occur until the Reset
Mode is cancelled again.
This register contains three status bytes in which the bits not related to transmission are
identical to the corresponding bits in the Global Status Register, while those relating to
transmission reflect the status of each of the 3 Tx Buffers.
Bit Symbol Function
7:0 EWL
Function
Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.
Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.
Transmit Buffer Status 1.
Software cannot access the Tx Buffer 1 nor write to the corresponding
CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a
message is either waiting for transmission or is in transmitting process.
Software may write a message into the Transmit Buffer 1 and its CANxTFI,
CANxTID, CANxTDA, and CANxTDB registers.
Transmission Complete Status.
The previously requested transmission for Tx Buffer 1 has been successfully
completed.
Receive Status. This bit is identical to the RS bit in the GSR.
address 0xE004 8018) bit description
During CAN operation, this value is compared to both the Tx and
Rx Error Counters. If either of these counter matches this value,
the Error Status (ES) bit in CANSR is set.
Rev. 04 — 26 August 2009
t
t
TSEG1
TSEG2
=
=
Chapter 18: LPC24XX CAN controllers CAN1/2
t
t
SCL
SCL
×
×
(
(
TSEG1
TSEG2
+
+
1
1
)
)
UM10237
© NXP B.V. 2009. All rights reserved.
Reset
Value
96
10
= 0x60 X
0
Reset
Value
0
1
1
1
487 of 792
0
RM
Set
RM
Set
0
1
x
0
(10)
(9)
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