LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 729
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
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LPC2458FET180,551
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UM10237_4
User manual
Table 670. Channel Control registers (DMACC0Control - address 0xFFE0 410C and
Table 32–671
burst sizes.
Table 671. Source or destination burst size
Bit
11:0
14:12 SBSize
17:15 DBsize
20:18 SWidth
23:21 DWidth
25:24 -
26
27
30:28 Prot
31
Bit value of DBSize or SBSize
000
001
010
011
Symbol
TransferSize Transfer size. A write to this field sets the size of the transfer
SI
DI
I
DMACC1Control - address 0xFFE0 412C) bit description
shows the value of the 3 bit DBSize or SBSize fields and the corresponding
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Description
when the GPDMA is the flow controller.A read from this field
indicates the number of transfers completed on the
destination bus. Reading the register when the channel is
active does not give useful information because by the time
that the software has processed the value read, the channel
might have progressed. It is intended to be used only when a
channel is enabled and then disabled.The transfer size value
is not used if the GPDMA is not the flow controller.
Source burst size. Indicates the number of transfers that
make up a source burst. This value must be set to the burst
size of the source peripheral, or if the source is memory, to
the memory boundary size. The burst size is the amount of
data that is transferred when the DMACBREQ signal goes
active in the source peripheral.
Destination burst size. Indicates the number of transfers that
make up a destination burst transfer request. This value must
be set to the burst size of the destination peripheral, or if the
destination is memory, to the memory boundary size. The
burst size is the amount of data that is transferred when the
DMACBREQ signal goes active in the destination peripheral.
Source transfer width. Transfers wider than the AHB master
bus width are illegal.The source and destination widths can
be different from each other. The hardware automatically
packs and unpacks the data as required.
Destination transfer width. Transfers wider than the AHB
master bus width are not supported.The source and
destination widths can be different from each other. The
hardware automatically packs and unpacks the data as
required.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Source increment. When set the source address is
incremented after each transfer.
Destination increment. When set the destination address is
incremented after each transfer.
Protection.
Terminal count interrupt enable bit. It controls whether the
current LLI is expected to trigger the terminal count interrupt.
Rev. 04 — 26 August 2009
Source or distention burst transfer request size
1
4
8
16
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
0
0
0
0
0
NA
0
0
0
0
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