LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 721

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
6.1.1 Interrupt Status Register (DMACIntStatus - 0xFFE0 4000)
6.1 General GPDMA registers
Table 652. Summary of GPDMA registers
[1]
[2]
This section describes the registers of the GPDMA.
The DMACIntStatus Register is read-only and shows the status of the interrupts after
masking. A HIGH bit indicates that a specific DMA channel interrupt request is active. The
request can be generated from either the error or terminal count interrupt requests.
Table 32–653
Name
DMACEnbldChns
DMACSoftBReq
DMACSoftSReq
DMACSoftLBReq
DMACSoftLSReq
DMACConfiguration
DMACSync
Channel 0 Registers
DMACC0SrcAddr
DMACC0DestAddr
DMACC0LLI
DMACC0Control
DMACC0Configuration
Channel 1 Registers
DMACC1SrcAddr
DMACC1DestAddr
DMACC1LLI
DMACC1Control
DMACC1Configuration
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Bit [17] is read-only.
shows the bit assignments of the DMACIntStatus Register.
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
Description
Enabled Channel Register
Software Burst Request
Register
Software Single Request
Register
Software Last Burst Request
Register
Software Last Single Request
Register
Configuration Register
Synchronization Register
Channel 0 Source Address
Register
Channel 0 Destination
Address Register
Channel 0 Linked List Item
Register
Channel 0 Control Register
Channel 0 Configuration
Register
Channel 1 Source Address
Register
Channel 1 Destination
Address Register
Channel 1 Linked List Item
Register
Channel 1 Control Register
Channel 1 Configuration
Register
Access Reset
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
0x0
0x0000
0x0000
0x0000
0x0000
0x0000 0000 0xFFE0 4030
0x0000
0x0000 0000 0xFFE0 4100
0x0000 0000 0xFFE0 4104
0x0000 0000 0xFFE0 4108
0x0000 0000 0xFFE0 410C
0x00000
0x0000 0000 0xFFE0 4120
0x0000 0000 0xFFE0 4124
0x0000 0000 0xFFE0 4128
0x0000 0000 0xFFE0 412C
0x00000
[1]
UM10237
[2]
[2]
© NXP B.V. 2009. All rights reserved.
Address
0xFFE0 401C
0xFFE0 4020
0xFFE0 4024
0xFFE0 4028
0xFFE0 402C
0xFFE0 4034
0xFFE0 4110
0xFFE0 4130
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