LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 555

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
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UM10237_4
User manual
Fig 107. Command path state machine
Fig 108. MCI command transfer
The timeout period has a fixed value of 64 MCICLK clocks period.
The CPSM remains in the IDLE state for at least eight MCICLK periods to meet Ncc and Nrc timing constraints.
MCICLK
State
MCICMD
PEND
LastData
When the WAIT state is entered, the command timer starts running. If the timeout
reached before the CPSM moves to the RECEIVE state, the timeout flag is set and the
IDLE
If the interrupt bit is set in the command register, the timer is disabled and the CPSM waits
for an interrupt request from one of the cards. If a pending bit is set in the command
register, the CPSM enters the PEND state, and waits for a CmdPend signal from the data
path subunit. When CmdPend is detected, the CPSM moves to the SEND state. This
enables the data counter to trigger the stop command transmission.
Figure 21–108
Pending command
IDLE
HI-Z
2
Enabled and
state is entered.
Disabled
command start
controller drives
Enabled and
COMMAND
SEND
shows the MCI command transfer.
SEND
Rev. 04 — 26 August 2009
no response
WAIT
Disabled or
HI-Z
response
Wait for
IDLE
RESPONSE
card drives
RECEIVE
Chapter 21: LPC24XX SD/MMC card interface
or timeout
Disabled
WAIT
command CRC failed
Response received
MCICLK
min 8
IDLE
HI-Z
or disabled or
controller drives
Response
COMMAND
RECEIVE
started
SEND
UM10237
© NXP B.V. 2009. All rights reserved.
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