LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 702

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
UM10237_4
User manual
6.3 Echo <setting>
6.4 Write to RAM <start address> <number of bytes>
Table 632. ISP Set Baud Rate command
Table 633. Correlation between possible ISP baudrates and CCLK frequency (in MHz)
[1]
Table 634. ISP Echo command
The host should send the data only after receiving the CMD_SUCCESS return code. The
host should send the check-sum after transmitting 20 UU-encoded lines. The checksum is
generated by adding raw data (before UU-encoding) bytes and is reset after transmitting
20 UU-encoded lines. The length of any UU-encoded line should not exceed
61 characters(bytes) i.e. it can hold 45 data bytes. When the data fits in less then
20 UU-encoded lines then the check-sum should be of the actual number of bytes sent.
The ISP command handler compares it with the check-sum of the received bytes. If the
check-sum matches, the ISP command handler responds with "OK<CR><LF>" to
Command
Return Code
Description
Example
ISP Baudrate .vs.
CCLK Frequency
10.0000
11.0592
12.2880
14.7456
15.3600
18.4320
19.6608
24.5760
25.0000
Command
Input
Return Code
Description
Example
ISP entry after reset uses the on chip IRC and PLL to run the device at CCLK = 14.748 MHz
[1]
B
CMD_SUCCESS |
INVALID_BAUD_RATE |
INVALID_STOP_BIT |
PARAM_ERROR
This command is used to change the baud rate. The new baud rate is effective
after the command handler sends the CMD_SUCCESS return code.
"B 57600 1<CR><LF>" sets the serial port to baud rate 57600 bps and 1 stop bit.
A
Setting: ON = 1 | OFF = 0
CMD_SUCCESS |
PARAM_ERROR
The default setting for echo command is ON. When ON the ISP command handler
sends the received serial data back to the host.
"A 0<CR><LF>" turns echo off.
Rev. 04 — 26 August 2009
Chapter 31: LPC24XX On-chip bootloader for flashless parts
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© NXP B.V. 2009. All rights reserved.
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