LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 355

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

NXP Semiconductors
Table 332. USB UDCA Head register (USBUDCAH - address 0xFFE0 C280) bit description
UM10237_4
User manual
Bit
6:0
31:7
Symbol
-
UDCA_ADDR
9.8.4 USB UDCA Head register (USBUDCAH - 0xFFE0 C280)
9.8.5 USB EP DMA Status register (USBEpDMASt - 0xFFE0 C284)
Software can also use this register to initiate a DMA transfer to proactively fill an IN
endpoint buffer before an IN token packet is received from the host.
USBDMARSet is a write only register.
The USBDMARSet bit allocation is identical to the USBDMARSt register
Table 331. USB DMA Request Set register (USBDMARSet - address 0xFFE0 C258) bit
The UDCA (USB Device Communication Area) Head register maintains the address
where the UDCA is located in the USB RAM. Refer to
communication area”
UDCA and DMA descriptors. USBUDCAH is a read/write register.
Bits in this register indicate whether DMA operation is enabled for the corresponding
endpoint. A DMA transfer for an endpoint can start only if the corresponding bit is set in
this register. USBEpDMASt is a read only register.
Table 333. USB EP DMA Status register (USBEpDMASt - address 0xFFE0 C284) bit
Bit
0
1
31:2 EPxx
Bit
0
1
31:2 EPxx_DMA_ENABLE
Description
Reserved. Software should not write ones to reserved bits. The UDCA is
aligned to 128-byte boundaries.
Start address of the UDCA.
Symbol
EP0_DMA_ENABLE
EP1_DMA_ENABLE
Symbol Value Description
EP0
EP1
description
description
0
0
0
1
and
Rev. 04 — 26 August 2009
Control endpoint OUT (DMA cannot be enabled for this endpoint
and the EP0 bit must be 0).
Control endpoint IN (DMA cannot be enabled for this endpoint and
the EP1 bit must be 0).
Set the endpoint xx (2 ≤ xx ≤ 31) DMA request.
No effect.
Set the corresponding bit in USBDMARSt.
Section 13–14.4 “The DMA descriptor”
Value Description
0
0
0
1
Control endpoint OUT (DMA cannot be enabled for
this endpoint and the EP0_DMA_ENABLE bit must
be 0).
Control endpoint IN (DMA cannot be enabled for this
endpoint and the EP1_DMA_ENABLE bit must be
0).
endpoint xx (2 ≤ xx ≤ 31) DMA enabled bit.
The DMA for endpoint EPxx is disabled.
The DMA for endpoint EPxx is enabled.
Chapter 13: LPC24XX USB device controller
Section 13–14.2 “USB device
for more details on the
UM10237
© NXP B.V. 2009. All rights reserved.
(Table
Reset value
0x00
0
13–328).
355 of 792
Reset
value
0
0
0
Reset
value
0
0
0