UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 187

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

uPSD34xx
28.1.5
28.1.6
28.1.7
program address space (accessed with PSEN) or XDATA space (accessed with RD or WR)
as defined with PSDsoft Express. The user only has to specify an address range for each
segment, and specify if Secondary Flash memory will reside in 8032 data or program
address space, and then PSEN, RD, or WR are automatically activated for the specified
range. 8032 firmware is easily programmed into Secondary Flash memory using PSDsoft
Express and others. See
SRAM
The SRAM is selected by a single signal, named RS0, from the Decode PLD. SRAM may be
located at any address within 8032 XDATA space (accessed with RD or WR). These choices
are specified using PSDSoft Express, where the user specifies an SRAM address range.
See
The SRAM may optionally be backed up by an external battery (or other DC source) to
make its contents non-volatile (see
on page
Table 101. uPSD34xx memory configuration
Runtime control registers, csiop
A block of 256 bytes is decoded inside the PSD Module for module control and status (see
Table 106 on page
sheet as csiop (Chip Select I/O Port), and is selected by the Decode PLD output signal,
CSIOP. The csiop registers are always viewed by the 8032 as XDATA, and are accessed
with RD and WR signals. The address range of csiop is specified using PSDsoft Express
where the user only has to specify an address range of 256 bytes, and then the RD or WR
signals are automatically activated for the specified range. Individual registers within this
block are accessed with an offset from the specified csiop base address. 39 registers are
used out of the 256 locations to control the output state of I/O pins, to read I/O pins, to set
the memory page, to control 8032 program and data address space, to control power
management, to READ/WRITE macrocells inside the General PLD, and other functions
during runtime. Unused locations within csiop are reserved and should not be accessed.
Memory page register
8032 MCU architecture has an inherent size limit of 64K bytes in either program address
space or XDATA space. Some uPSD34xx devices have much more memory that 64K, so
special logic such as this page register is needed to access the extra memory. This 8-bit
page register
registers. Page register outputs feed directly into both PLDs creating extended address
uPSD3422
uPSD3433
uPSD3434
uPSD3454
Device
Table 101 on page 187
250).
(bytes)
Flash
Total
Size
(Figure
128K
256K
256K
64K
199). The base address of these 256 locations is referred to in this data
Main Flash Memory
Individual
63) can be loaded and read by the 8032 at runtime as one of the csiop
(bytes)
Sector
Size
16K
16K
32K
32K
Table 101 on page 187
for SRAM sizes.
Select Signal)
Number of
Section 28.5.62: SRAM standby mode (battery backup)
Sectors
(Sector
4 (FS0-3)
8 (FS0-7)
8 (FS0-7)
8 (FS0-7)
(bytes)
Flash
for Secondary Flash sector sizes.
Total
Size
32K
32K
32K
32K
Secondary Flash Memory
Individual
(bytes)
Sector
Size
8K
8K
8K
8K
(Sector Select
4 (CSBOOT0-3)
4 (CSBOOT0-3)
4 (CSBOOT0-3)
4 (CSBOOT0-3)
Number of
Sectors
Signal)
PSD module
(bytes)
SRAM
SRAM
187/293
Size
32K
4K
8K
8K