UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 207

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

uPSD34xx
28.5.11
attempted to program bit to logic ’1’ when that bit was already programmed to logic ’0’ (must
erase to achieve logic ’1’).
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the byte that was written to the Flash
memory with the byte that was intended to be written.
When using the Data Polling method during an erase operation,
However, the Data Polling Flag Bit (DQ7) is '0' until the erase operation is complete. A ’1’ on
the Error Flag Bit (DQ5) indicates a time-out condition on the Erase cycle, a ’0’ indicates no
error. The 8032 can read any location within the sector being erased to get the Data Polling
Flag Bit (DQ7) and the Error Flag Bit (DQ5).
Figure 72. Data polling flowchart
Data Toggle
Checking the Toggle Flag Bit (DQ6) is another method of determining whether a program or
erase operation is in progress or has completed.
algorithm.
When the 8032 issues a program instruction sequence, the embedded algorithm within the
Flash memory array begins. The 8032 then reads the location of the byte to be programmed
in Flash memory to check status. The Toggle Flag Bit (DQ6) of this location toggles each
time the 8032 reads this location until the embedded algorithm is complete. The 8032
continues to read this location, checking the Toggle Flag Bit (DQ6) and monitoring the Error
Flag Bit (DQ5). When the Toggle Flag Bit (DQ6) stops toggling (two consecutive reads yield
the same value), then the embedded algorithm is complete. If the Error Flag Bit (DQ5) is '1,'
at VALID ADDRESS
NO
READ DQ5 & DQ7
READ DQ7
START
DATA
DATA
FAIL
DQ7
DQ5
DQ7
= 1
=
=
YES
NO
NO
YES
YES
Figure 73
PASS
shows the Data Toggle
AI01369B
Figure 72
still applies.
PSD module
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