UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 257

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

uPSD34xx
28.6.8
Figure 95. Example of chaining uPSD34xx devices
Debugging the 8032 MCU module
The 8032 on the MCU module may be debugged in-circuit using the same four basic JTAG
signals as used for JTAG ISP (TDI, TDO, TCK, TMS). The signals TSTAT and TERR are not
needed for debugging, and they will not create a problem if they exist on the circuit board
while debugging. The same connector specified in
ISP or for 8032 debugging. There are 3rd party suppliers of uPSD34xx JTAG debugging
equipment (check www.st.com/psm). These are small pods which connect to a PC (or
notebook computer) using a USB interface, and they are driven by an 8032 Integrated
Development Environment (IDE) running on the PC.
Standard debugging features are provided through this JTAG interface such as single-step,
breakpoints, trace, memory dump and fill, and others. There is also a dedicated Debug pin
(shown in
devices upon a programmable internal event (e.g., breakpoint match), or the pin can be
configured as an input so an external device can initiate an internal debug event (e.g., break
execution). The Debug pin function is configured by the 8032 IDE debug software tool. See
Section 12: Debug unit on page 50
The Debug signal should always be pulled up externally with a weak pull-up (100K
minimum) to V
Figure 93 on page
Connects Here
Programming
Equipment
or Test
JTAG
Figure 91 on page
CC
even if nothing is connected to it, as shown in
TSTAT
TERR
TMS
GND
255.
TDO
TCK
RST
V
TDI
CC
CONN.
JTAG
Optional
Optional
10K
253) which can be configured as an output to trigger external
Circuitry
System
Reset
for more details.
100K
100K
100K
100K
100K
Figure 94 on page 256
100K
Figure 92 on page 254
TMS
TDO
TMS
TCK
TDI
TDO
TCK
TMS
TCK
TDI
TDO
TDI
TSTAT
TERR
TSTAT
TERR
CIRCUIT BOARD
Device 2
Device N
Device 1
IEEE 1149.1
can be used for
Compliant
uPSD34xx
µPSD34xx
Device
PSD module
257/293
AI10459
and