UPSD3433EB40U6 STMicroelectronics, UPSD3433EB40U6 Datasheet - Page 56

• Manufacturer Part Number: UPSD3433EB40U6
• Description: MCU 8BIT 8032 128KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433EB40U6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5660

Interrupt system
13.1.8
13.1.9
Note:
56/293
1
PCA interrupt
The PCA has eight interrupt sources, which are logically ORed together when interrupting
the MCU.The ISR must read the flag bits to determine the cause of the interrupt.
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●
Tables
SFRs.
USB Interrupt
The USB interrupt has multiple sources. The ISR must read the USB Interrupt Flag
Registers (UIF0-3) to determine the source of the interrupt.
The USB interrupt can be activated by any of the following four group of interrupt sources:
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Table 17.
1 = Enable Interrupt, 0 = Disable Interrupt
Bit 7
5
4
3
2
1
0
EA
Bit
Each of the six TCMs can generate a "match or capture" interrupt on flag bits OFV5..0
respectively.
Each of the two 16-bit counters can generate an overflow interrupt on flag bits INTF1
and INTF0 respectively.
Global: the interrupt flag is set when any of the following events occurs: USB Reset,
USB Suspend, USB Resume, and End of Packet;
In FIFO: the interrupt flag is set when any of the End Point In FIFO becomes empty;
Out FIFO: the interrupt flag is set when any of the End Point Out FIFO becomes full;
and
In FIFO NAK: the interrupt flag is set when any of the End Point In FIFO is not ready for
an IN (in-bound) packet.
7
6
(1)
(1)
(1)
(1)
(1)
(1)
17
through
IE: interrupt enable register (SFR A8h, reset value 00h)
Symbol
Bit 6
ET2
ES0
ET1
EX1
ET0
EX0
EA
–
–
Table 20 on page 58
Bit 5
R/W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
ET2
Enable Timer 2 Interrupt
Enable Timer 1 Interrupt
Enable Timer 0 Interrupt
Global disable bit. 0 = All interrupts are disabled. 1 = Each
interrupt source can be individually enabled or disabled by
setting or clearing its enable bit.
Do not modify this bit. It is used by the JTAG debugger for
instruction tracing. Always read the bit and write back the
same bit value when writing this SFR.
Enable UART0 Interrupt
Enable External Interrupt INT1
Enable External Interrupt INT0
Bit 4
ES0
have detailed bit definitions of the interrupt system
Bit 3
ET1
Function
Bit 2
EX1
Bit 1
ET0
uPSD34xx
Bit 0
EX0